1. 1. Introduction

Recently the strong need for ultrahigh-speed logic devices^{[1, 2, 3]} has driven complementary metal-oxide-\break semiconductor (CMOS) researchers to search for alternative substrates including III-V compound semiconductors such as GaAs,InP,and InGaAs due to their high electron mobility,high injection velocity,and low power consumption^{[4, 5, 6, 7, 8]}. However,the most challenging problem for the III-V based metal-oxide-semiconductor field effect transistor (MOSFET) is the Fermi-level pinning^{[9, 10, 11]} due to the large density of defect states within the GaAs band gap opposing the formation of an inversion in the channel. Furthermore,large amounts of native oxides including As oxides (As$_{2}$O$_{3}$ and As$_{2}$O$_{5})$ and Ga$_{2}$O$_{3}$ contribute to high interface trap density ($D_{\rm it})$ on GaAs^{[12, 13, 14]},so the removal of interfacial oxides at the high $k$/GaAs interface is a key factor for achieving high performance MOS transistor operation. Meanwhile,the continuous MOSFET size scaling leads to an inevitably high gate leakage,which limits the maximum drain current and noise margin,thereby severely degrading the flexibility of the circuit design and hindering the CMOS low consumption application^{[15, 16, 17]}.

In order to obtain a better interface quality as well as lower gate leakage,we have systematically investigated in this study the role of the temperature during ALD and annealing in determining the interfacial and electrical properties of Al/HfO$_{2}$/p-GaAs MOS capacitors. Detailed analysis of current-voltage ($I$-$V$) measurements has been demonstrated to show the effect of ALD and annealing temperature on the gate dielectric properties. In addition,monochromatic X-ray photoelectron spectroscopy (XPS) has also been used to provide a comprehensive understanding of the temperature controlled reaction at the HfO$_{2}$/p-GaAs interface.

2. 2. Experiment

The GaAs wafers used in this study were single-polished,p-type (100) oriented,Zn-doped with a doping concentration of 5 $\times$ 10$^{16}$ cm$^{-3}$. Prior to deposition,the samples were firstly rinsed using acetone,isopropanol and DI water,then soaked in HCl for 1 min for native oxide removal,and finally dipped in (NH$_{4})$$_{2}$S (10%) for 1 min to passivate elemental As^[18]. Then the pre-treated substrates were loaded inside the ALD chamber for HfO$_{2}$ dielectric deposition using TEMAH (Hf precursor) and H$_{2}$O (oxygen precursor). The growth temperature was set as 200,250,and 300 ℃,respectively. The ALD process has been discussed in detail in the previous paper^[19]. The physical thickness of HfO$_{2}$ was measured to be 3.1 nm by Sopra GES$_{5}$E spectroscopic ellipsometry. Then the post deposition annealing (PDA) process was carried out by rapid thermal annealing (RTA) at 400,500,and 600 ℃ for 1 min under N$_{2}$ ambient. Control samples without PDA were also fabricated. Finally,a MOS capacitor structure was produced by fabricating an Al gate electrode using the lift-off method followed by e-beam evaporating Ti (20 nm)/Au (150 nm) metal stack as the backside ohmic contact. The e-beam evaporated Al electrode was a circle with an area of $\sim$5.8 $\times$ 10$^{-3}$ cm$^{2}$ and a thickness of 200~nm. The chemical structure of the interface between HfO$_{2}$ and p-GaAs was analyzed by XPS using a monochromatic Al K$\alpha$ X-ray source (1486.7 eV) with a line width of 0.25 eV and a take-off angle (TOA) of 45$^\circ$[20,21]. The XPS spectra were compensated with a C 1s binding energy of 284.8 eV and then carefully deconvoluted using the Avantage software^[22]. All XPS fits included a Shirley background subtraction and kept the full width half maximum (FWHM) of specific core-level features unchanged^[23]. The HP 4156B semiconductor parameter analyzer was used for $I$-$V$ characterizations.

3. 3. Results and discussion

According to our results published in the previous paper,it can be concluded that better interface quality can be achieved at a higher ALD temperature^[19]. In addition,a more intensive study on the relationship between dielectric leakage properties and ALD temperature will be discussed in the following.

Figure1 illustrates the $I$-$V$ characteristics of p-GaAs MOS capacitors with HfO$_{2}$ deposited at different ALD temperatures without annealing. The leakage current decreases with the increase of ALD temperature and the lowest leakage current is obtained at 300 ℃. From the previous XPS analysis,it can be concluded that the lowest amount of interfacial oxides is achieved at the interface for 300 ℃ resulting in the lowest $D_{\rm it}$. However,there are large amounts of Ga-O and As-O bonds for 200 and 250 ℃^[19]. So,the Frenkel-Poole emission dominates the leakage current because of the bad interface between HfO$_{2}$ and GaAs at a lower ALD temperature[24,\,25]. However,the Frenkel-Poole conduction diminishes greatly and leads to the evident reduction of gate leakage current for ALD at 300~℃ because of the interface improvement due to the enhanced "self-cleaning" effect^[26]. The Schottky emission mechanism presumably dominates in this case as the GaAs/HfO$_{2}$ barrier height is just 1.47 eV^[27]. In general,the difference of leakage current with ALD temperature is consistent with the previous capacitance-voltage (C-V) measurements and XPS result^[19].

Figure  1.  $I$-$V$ characteristics of Al/HfO$_{2}$/p-GaAs MOS capacitors for different ALD temperatures without annealing.

DownLoad: Full-Size Img PowerPoint

Figure2 shows the $I$-$V$ characteristics after annealing HfO$_{2}$ layer with different PDA temperatures for ALD at 300℃. It can be observed that the lowest leakage current is obtained for 500℃ annealing. Up to 500 ℃,the densification effect of the HfO$_{2}$ dielectric dominates and improves the dielectric properties^[28]. So,the leakage current decreases until 500℃. However,high temperature annealing above 500~℃ results in the crystallization of the high-$k$ dielectric,which produces grain boundaries that serve as high leakage paths in the gate oxide^[29]. Moreover,annealing at 600 ℃ accelerates the diffusion of Ga and As elements into the HfO$_{2}$ layer,severely degrading the dielectric properties thus lead to a jump in leakage current^[28]. The $I$-$V$ measurements clearly show that 500℃ is the optimum PDA temperature to obtain good dielectric properties. In the following,a further study will be performed using XPS on the reaction chemistry of interfacial oxides for samples annealing at 500℃ after different temperatures of ALD.

Figure  2.  $I$-$V$ characteristics after annealing HfO$_{2}$ on p-GaAs with different PDA temperatures for ALD at 300 ℃.

DownLoad: Full-Size Img PowerPoint

Figure3 shows As 3d spectra for HfO$_{2}$ deposited on GaAs and subjected to a (500℃,1 min) PDA. The peaks due to arsenic oxides,As$_{2}$O$_{5}$ and As$_{2}$O$_{3}$,are at binding energies of 45.0 and 44.2 eV,respectively,while the doublet peak at 40.8 eV is assigned as As-Ga bonding taking into account the spin-orbit splitting using an intensity ratio of 3 : 2 and a separation of 0.69~eV^[30]. It is interesting to observe that for an ALD temperature of 200,250,or 300 ℃,residual arsenic oxides^[19] decrease evidently after annealing at 500 ℃,and for 300 ℃ treated samples,almost no arsenic oxides are detected. This suggests that the residual arsenic oxides after ALD are consumed during PDA.

Figure  3.  As 3d core-level spectra of GaAs after annealing HfO$_{2}$ at 500 ℃ for different ALD temperatures.

DownLoad: Full-Size Img PowerPoint

On the contrary,the Ga 2p$_{3/2}$ spectra shows a proportional increase in the Ga$_{2}$O$_{3}$ peak at a binding energy of 1118.26 eV^[31] compared with control samples^[19] after annealing as indicated in Figure4. The amount of Ga$_{2}$O$_{3}$ is detected in the smart mode of the Avantage software as 82.07%,75.90%,and 49.84%,respectively after annealing and the corresponding increment compared with control samples^[19] is 13.66%,10.03%,and 6.39%,respectively for ALD temperatures of 200 ℃,250 ℃,and 300 ℃,respectively as shown in Figure4(b). It can be concluded that more Ga$_{2}$O$_{3}$ after PDA is closely related to the consumption of As oxides via an exchange reaction in which As oxides react with the GaAs substrate and convert to Ga$_{2}$O$_{3}$ as shown in Equation (1)^[32]:

Figure  4.  XPS Ga 2p$_{3/2}$ spectra analysis of GaAs after annealing HfO$_{2}$ at 500 $\du$ for different ALD temperatures. (a) Ga 2p$_{3/2}$ core-level spectra. (b) Plot of the percentage and percentage increment of Ga$_{2}$O$_{3}$ after annealing versus ALD temperature.

DownLoad: Full-Size Img PowerPoint

Thus,an insignificant reduction of As oxides during ALD at 200 ℃ results in more Ga$_{2}$O$_{3}$ at the interface after PDA,while an obvious reduction during ALD at 300 ℃ leads to the least Ga$_{2}$O$_{3}$ formation after PDA.

4. 4. Summary

In summary,we have studied the temperature dependent characteristics during ALD and annealing in Al/HfO$_{2}$/p-GaAs MOS capacitors using TEMAH as the precursor. The leakage current for ALD at 300 ℃ is the lowest,as the Frenkel-Poole emission which dominates the leakage current in the presence of a large amount of defect states is greatly weakened due to the improvement of the interface quality at a higher temperature. $I$-$V$ measurements also indicate that 500 ℃ is the optimum PDA temperature to obtain the lowest leakage current compared with other annealing temperatures. Meanwhile,annealing of HfO$_{2}$ at 500 ℃ decomposes the residual As$_{2}$O$_{3}$ after ALD and forms Ga$_{2}$O$_{3}$ via an exchange reaction. It is reasonable to conclude that ALD growth of HfO$_{2}$ at 300 ℃ using the TEMAH precursor followed by annealing at 500 ℃ provides a feasible way to obtain a good high-$k$/GaAs interface as well as preferable dielectric properties suitable for future III-V MOS applications.

Acknowledgment

The authors would like to acknowledge the contributions of Professor ZHANG David Wei in Fudan University and Mr. FANG Run-Chen in Arizona State University for their ALD deposition work.