1. Introduction

Since the S band is widely utilized for radar communications,solid-state power amplifiers (PAs) are one of the most important and critical elements of the radio frequency front-end. Since multiple PAs are used in phased-array radar,there is an urgent need to increase the efficiency of PA to reduce the power consumption of radar systems^[1]. Considering the atmospheric absorption and attenuation in transmittance,a large output power of PAs is also desirable for T/R module applications. Furthermore,energy is one of the most critical issues in modern society,and green eco technologies are required^[2],so that more attention is paid to propagating solar power efficiently by using solar transmits satellite (SPS) and PAs are required with a high-power conversion efficiency^[3].

In a common case to improve the output power and efficiency,PAs are typically operated under large-signal regimes. However,this will produce significant harmonic components because of the inherent non-linearity of transistors. Besides,more power is dissipated and the adjacent channels are interfered if the harmonics are not suppressed properly. To solve the above problems,many works for harmonic suppression have been published^{[4, 5, 6, 7, 8, 9]}. Nonetheless,these techniques are not suitable for high-integration operation due to the cost and size considerations.

In order to enhance the efficiency of PAs,it is effective to bias the device to a low quiescent point and provide suitable impedance at desirable harmonics. A class-F PA is useful to achieve high efficiency by shaping the output voltage in the shape of a square via a special matching circuit^{[10, 11]}. Many works have been reported for the broadband operation^{[12, 13]},but most of them are complex and cumbersome for the reality of RFIC.

This paper presents a broadband class-F PA for S band application with high-order harmonic suppression by using a new matching technique. The circuit topology and matching operation are explained. The on-chip implementations through the HBT process are demonstrated. The measured results show that the proposed PA is not only highly efficient,but also leads to high performance with harmonic suppression.

2. Broadband class-F PA with refinement of harmonic suppression matching network

In the ideal switching stage of PA,the output matching circuit provides a high impedance terminal at all odd harmonics and shorts at all even harmonics. The voltage waveform has only odd harmonics,whereas the current waveform stands only even harmonics^[11],thus the overlap region of voltage and current can be reduced and less power loss would be dissipated in the transistors. Such a circuit is called a class-F stage. Nevertheless,it is impossible to control all the harmonics while meeting the reality requirements in terms of cost and size,thus limited harmonics are controlled in this proposed work.

The overall schematic diagram of the realized broadband matched class-F PA is shown in Figure1,and the shadow region within which the components are integrated on chip. Generally,in order to achieve large output power,the area of the power stage is dramatically large and sustains a large parasitic capacitance,$C_{\rm c}$. Several serial resonant circuits (harmonics trap),consisting of $L_{2}$ and $C_{2}$,$L_{3}$ and $C_{3}$,as well as $L_{5}$ and $C_{5}$,are immersed into the output matching circuit to eliminate the second,third and fifth harmonics,respectively. The second harmonic trap is shunted at the device while the third and fifth harmonics traps are immersed into the two-stage L-sections fundamental matching circuit for broadband operation.

In a common case to convert the impedance of the load to the optimum resistor of the PA,the matching circuit is connected between the output of the die and the load. The basic configuration of the broadband matching circuit with two L-sections and harmonic suppression traps is illustrated in Figure~2(a). The second harmonic trap is equivalent to an inductance at the third and five harmonic frequencies,but with a capacitor at the fundamental frequency,so that it can be cancelled by the shunt connected parallel circuit,$L_{\rm C}$ and $C_{\rm c}$,and the fundamental impedance is constant across the bandwidth because of the impact of the two L-sections matching network. The third and fifth harmonic traps are equivalent to a capacitance at the operation frequency and are represented by the labels $C_{3,\,0}$ and $C_{5,\,0}$,respectively,so the equivalent circuit at fundamental frequency can be illustrated in Figure2(b).

As depicted in Reference [14],the value of quality factor $Q$ is given as $$\begin{equation} \label{eq1} Q=\sqrt {\sqrt {\frac{R_{\rm L}}{R_{\rm opt} }} -1} , \end{equation}$$ where $R_{\rm L}$ is the load impedance,$R_{\rm opt}$ is the optimal impedance of the class-F PA,and the parameter of the matching network can be expressed as: $$\begin{equation} \label{eq2} C_3 =\frac{8}{9} \frac{Q}{\omega _0 R_{\rm opt}},\quad L_3 =\frac{1}{(3\omega _0 )^2C_{3} }, \end{equation}$$ $$\begin{equation} \label{eq3} C_5 =\frac{24}{25} \frac{Q}{\omega _0 R_{\rm L} },\quad L_5=\frac{1}{(5\omega _0 )^2C_5}, \end{equation}$$ $$\begin{equation} \label{eq4} L_1 =\frac{8}{9} \frac{Q^2}{C_3 \omega _0 ^2(1+Q^2)}, \end{equation}$$ $$\begin{equation} \label{eq5} L_4 =\frac{24Q^2}{25C_5 \omega _0 ^2(1+Q^2)}, \end{equation}$$ where the $\omega_{0}$ is the operating angular frequency. For the third harmonic condition,the second harmonic trap is equivalent to an inductance while the third harmonic trap provides near zero impedance. Consequently,the two-stage L-sections circuit can be equivalent to a pure inductance,and the equivalent circuit of the matching circuit can be illustrated in Figure2(c).

((1))

Thus,the output impedance can be derived as: $$\begin{equation} \label{eq6} Z_{\rm out} =X_{2,\,3\omega _0 } \vert \vert X_{c,\,3\omega _0 } \vert \vert X_{L_{\rm c},\,3\omega _0 } \vert \vert X_{1,\,3\omega _0 } =\infty , \end{equation}$$ where \left\{ { $$\begin{array}{*{20}{l}} {{X_{2,{\kern 1pt} 3{\omega _0}}} = {\text{j}}\frac{5}{{12{\omega _0}{C_2}}};} \\ {[2mm]{X_{1,{\kern 1pt} 3{\omega _0}}} = {\text{j}}3{\omega _0}{L_1},} \\ {[2mm]{X_{{L_{\text{c}}},3{\omega _0}}} = {\text{j}}3{\omega _0}{L_{\text{c}}};} \\ {[2mm]{X_{{\text{c}},{\kern 1pt} 3{\omega _0}}} = \frac{1}{{{\text{j}}3{\omega _0}{C_{\text{c}}}}}.} \end{array}$$ } \right.

((6))

Substituting Equation (6) to Equation (7),the value of $C_{2}$ can be given as $$\begin{gathered} {C_2} = \frac{{{L_1} - {L_{{\text{eq}}}}}}{{{{(3{\omega _0})}^2}{L_1}{L_{{\text{eq}}}}}}; \hfill \\ {L_2} = \frac{1}{{{{(2{\omega _0})}^2}{C_2}}},\hfill \\ \end{gathered}$$ where $$\begin{equation} \label{eq9} L_{\rm eq} =\frac{L_{\rm c}}{(3\omega _0 )^2L_{\rm c} C_{\rm c} -1}, \end{equation}$$ where $L_{\rm c}$ is the choke inductance whose modulus is at least 10~times bigger than the fundamental impedance $R_{\rm opt}$.

((8))

Considering the large output power across S-band frequency,the realized circuit of class-F PA shown in Figure1 consists of a gain stage,drive stage and power stage to obtain a high gain performance. Power control,linearization,stability and flatness are concerned for tradeoff when designing the bias circuit^[10]. The gain stage is biased to a quiescent point beyond the light class AB condition for high linearity,and respectively deep class AB for the drive stage with a half-wave rectified output voltage,so that high gain and high efficiency performance can be obtained from the power stage^[10].

Such an amplifier,ideally,having a maximally flat third harmonically enhanced square wave for RF voltage,and a half wave rectified sine wave for RF current,is simulated with the configurations shown in Figure1 and is illustrated in Figure3. The current waveform with a slight clip-shaped peak is acquired by biasing the power stage near its threshold point. Since the action of the device knee voltage would generate substantial amounts of third harmonic,thus the current waveform is not performed as an ideal half-wave rectified sine wave. However,it is helpful to recover the peak current by introducing more high-order odd harmonics terminal with open circuit configurations,so that the current waveform nearly contains no odd harmonics and remains ideally half-sinusoidal.

The voltage waveform is bifurcated because not all the odd harmonics meet an open-circuited terminal and a short-circuited terminal for all even harmonics. Considering the power of higher harmonics is so low that it can be ignored,the bifurcated voltage waveform nearly contains no even harmonics,but it can be substantially shaped and remains ideally square wave when it employs more high-order harmonics matching schemes in which more even harmonics are shorted and odd harmonics are presented with an open-circuit. The simulated result of the output matching circuit is shown in Figure~4. The impedances are constant across 1.8 to 2.5 GHz,near zero across 3.6 to 5 GHz and near high pure reactance across 5.4 to 7.7 GHz. The simulated result of $S_{21}$ is shown in Figure5. Three null points at 4,6 and 10 GHz,which are caused by the harmonic short circuits,are attained. This shows that the class-F PA discussed so far has a good performance for the harmonic suppression.

3. Fabrication and measurement

As an experimental vehicle for the proposed power amplifier architecture,the class-F PA is fabricated by an InGaP/GaAs HBT process and integrated in a chip with the die size of 3 $\times$ 3 $\times$ 0.82 mm$^{3}$ as shown in Figure6,and the microphotograph is shown in Figure7.

The PA was tested under a CW input signal at 2 GHz and a supply voltage ($V_{\rm CC})$ of 5 V and a bias reference voltage ($V_{\rm ref})$ of 3.3 V. To achieve a sufficient linearity margin across the entire power range,it is desirable to set a high bias at the low power region. The bias currents of the power,driver and gain stages were 113,65 and 40 mA,respectively. The output matching circuit is fabricated on the FR4 PCB for tunability. All the inductors are implemented by bonding wires except $L_{4}$,$L_{3}$ and $L_{5}$. The inductance,$L_{4}$,is implemented by a transmission line for the broadband operation,and the back-via's parasitic inductance is used for $L_{3}$ and $L_{5}$ whose value is actually very small.

The large-signal S-parameters were measured as shown in Figure8,and Figure9 shows the gain and PAE at 2 GHz with a CW signal input. The ripple of the output power gain is within $\pm$0.5 dB. The PAE is about 57% at the peak of the output power. The performance of the harmonic suppression is shown in Figure10,and good harmonic power levels of less than -53 dBc are obtained at among second,third,fourth and fifth harmonics. Table1 compares the performances between this work,class-F,and the previously published works,conventional class-E and Doherty PA^{[5, 6, 7]}. The measured efficiency and harmonics suppression are excellent among the summarized reports.

4. Conclusions

This paper presents a broadband class-F PA for S-band applications with three stage constructions. Harmonic suppression circuits are completely merged into the output matching circuit. The PA is fabricated by an InGaP/GaAs HBT process and delivers a power gain of 35 dB with a ripple within $\pm$0.5~dB,and a PAE of 57% at the peak of output power. The power levels across the second to fifth order harmonic are all less than -53 dBc.