1. Introduction

Technological advancement in semiconductor industry has been witnessing aggressive scaling for improved speed and functionality. Although the continuous scaling is cost effective with reduced power dissipation and gate delays,it has increased the challenges faced by interconnect delay in very large-scale integrated (VLSI) circuits. Thus,two-dimensional integrated circuits (2D ICs) lose their suitability for nano feature sized devices while technology heads towards more than Moore's law. Due to the limited number of I/O pins and longer interconnects between die-to-die,the 2D IC integration offers lower bandwidth and hence degrades the system performance^[1].

In 3D integration,unlike 2D integration the power and clock signals are not required to traverse the whole chip and hence the signals are enabled to move through vertical interconnects. Therefore,3D integration scales down the longest global wires that reduce the overall chip area,transmission delay,power dissipation and offers high transistor packing density^[2]. A 3D IC offers various benefits such as improved silicon chip coverage and component velocity,reduced signal transmission delay^[3],small form factor,improved yield and reliability,reduced cost^[4] and risk of reverse engineering,improved bandwidth and heterogeneous integration capabilities^[5].

TSVs have distinct merits to make them promising technology for high-density 3D packaging. It is the core technology of 3D ICs that provides vertical interconnection ``VIA'' that passes completely through the silicon wafer or die^{[6, 7]}. It reduces the overall interconnect length and propagation delay among the stacked dies. TSVs have emerged as the future of 3D ICs as they have numerous advantages over traditional interconnection techniques^[6]. The TSV technology facilitates implementing heterogeneous platforms with a large number of functions including logic,memory chips,RFIC (radio frequency integrated circuit),analog/digital ICs,sensor chips,optoelectronics and MEMS (micro-electro mechanical systems)^[8]. Apart from this,TSV provides an improved I/O channel bandwidth^[9]. Attributable to such merits,TSV has become a major research topic of its time. However,TSVs also have some limitations that put utmost challenges to bring them forward in practical applications that lie in designing,manufacturing and cost effective parameters.

The performance of 3D ICs is strongly dependent on filler material. The different materials such as copper (Cu),tungsten (W),polysilicon and conductive polymer pastes are used as filler material for TSVs integrated on Si substrate. Cu has shown remarkable properties as filler material in TSVs due to its high electrical conductivity,well-established electrochemical decomposition (ECD) process and good thermal characteristics. However,some major limitations prevent it from being used for high aspect ratio TSV. Electromigration,higher resistivity^[10],on chip metal temperatures and the presence of a highly diffusive barrier layer with physical scaling are a few of them. However,these problems can be easily overcome using carbon nanotube (CNT) as TSV filler material. The unique properties of CNTs include higher current carrying capability,thermal stability and improved electromechanical as well as chemical properties. Moreover,being scalable to nanometer dimensions with large aspect ratios^[11],CNTs also help in overcoming the challenges such as electromigration,noise and propagation delays that have become major bottlenecks in gigascale integration (GSI). CNTs are seamlessly rolled up graphene sheets of nanometer range wherein edges are joined together to form a tube-like structure^[12]. Based on the number of concentrically rolled up graphene sheets,CNTs are categorized to single-walled (SWCNT) and multi-walled CNTs (MWCNT). CNTs are metallic as well as semiconducting depending on the chirality,i.e.,the rolled up direction of graphene sheets^[13]. An armchair configuration leads always to metallic tubes while a zigzag configuration can be metallic or semiconducting in nature^[12].

This paper analyzes and compares the propagation delay and power dissipation of SWCNT bundled TSVs having different bundle aspect ratio. Depending on the physical configuration,an equivalent electrical model of CNT bundled TSV is employed to represent the via line of a driver-TSV-load (DTL) system. For a fixed via height,the propagation delay and power dissipation are analyzed for different via radius and cross-sectional area.

3. Configuration and electrical model of SWCNT bundled TSV

3D integration is multiple stacking of heterogeneous technologies,functional components and disparate signals on multiple tiers^{[14, 15]} as shown in Figure 1. 3D ICs are the best suited for fabrication of stacked and vertically interconnected device layers^[8]. These layers are linked internally through silicon vias (TSVs) as shown in Figure 2.

The stacking of TSV on Si substrate primarily uses a SWCNT bundle as filler material. A dielectric layer of SiO$_{2}$ is used to surround the TSV for DC (direct current) isolation^[16]. The physical configuration of a pair of TSVs on Si substrate is shown in Figure 3 and their associated physical and geometrical parameters are shown in Table 1.

Depending on the physical configuration,an equivalent electrical circuit model of signal-ground SWCNT bundled TSV is shown in Figure 4. The via parasitics of the $RLC$ model are primarily dependent on the total number of SWCNTs ($N_{\rm CNT})$ in the bundle. The $N_{\rm CNT}$ primarily depends on the radius of the via ($r_{\rm via})$ and the SWCNT ($r_{\rm CNT})$ and can be expressed as

$N_{\rm CNT} \approx \frac{2\pi r_{\rm via}^2 }{\sqrt 3 (2r_{\rm CNT} +d_{\rm CNT} )^2}.$

(1)

The total number of conducting channels ($N_{\rm Total})$ is mainly dependent on the total conductive CNTs ($N_{\rm CNT})$ in a bundle and $N_{\rm Channel}$. Depending on the spin and sub-lattice degeneracy of carbon atoms,the $N_{\rm Channel}$ of each SWCNT is considered as 2$F_{\rm M}$. In case of via applications,the metallic CNTs are considered as conducting in nature. Therefore,using different metallic-to-semiconducting ratio $F_{\rm M}$ $=$ 1/3,2/3 and 1,the $N_{\rm Total}$ can be expressed as Equation (2). However,this research work considers $F_{\rm M}$ $=$ 1/3 that can be considered as a realistic scenario in the current fabrication process^{[17, 18]}.

$N_{\rm Total} =N_{\rm Channel} N_{\rm CNT} .$

(2)

The equivalent model of Figure 4 comprises of three different types of resistance: (1) quantum resistance ($R_{\rm Q}$ $=$ $h/2e^{2}$ $\approx$ 12.9 k$\Omega )$ that is due to the quantum confinement of carriers in a nanowire^{[19, 20]},(2) imperfect metal-nanotube contact resistance ($R_{\rm C}$ $=$ 3.2 k$\Omega )$ that is used to model the lumped resistance due to scattering at metal contacts and is dependent on the diameter of CNTs,and (3) scattering resistance ($R'_{\rm TSV})$ that is due to the static impurity scattering,defects,line edge roughness scattering (LER) and acoustic phonon scattering. The $R'_{\rm TSV}$ primarily depends on the mean free path^[21] and can be expressed as

$R'_{\rm TSV} =\frac{R_{\rm Q} }{2N_{\rm Total} \lambda _{\rm mfp} }.$

(3)

The equivalent inductance ($L'_{\rm TSV})$ of the electrical model of Figure 4 primarily comprises of (1) kinetic inductance ($L'_{\rm K})$ that originates from kinetic energy of electrons and (2) magnetic inductance ($L'_{\rm M})$ that is due to the magnetic field induced by the current flowing through a nanotube^[22]. The $L'_{\rm TSV}$,$L'_{\rm K}$ and $L'_{\rm M}$ in per unit height ($p.u.h.)$ can be expressed as

$L'_{\rm TSV} =\frac{L_{\rm K}' }{2N_{\rm Total} }+L_{\rm M}' ,$

(4)

where

$L'_{\rm M} =\frac{\mu _0 \mu _{\rm r} }{2\pi }\ln \frac{H_{\rm TSV} }{2r_{\rm CNT} },$

(5)

and

$L_{\rm K}' =\frac{h}{2e^2v_{\rm F} }.$

(6)

The mutual magnetic inductance has often been ignored in comparison to kinetic inductance ($L'_{\rm K})$ by several researchers. As reported by Sarto \textit{et al}.^[23] and Li \textit{et al}.^[24],the magnitude of $L'_{\rm K}$ is in the order of nH/$\mu$m whereas the mutual magnetic inductance is just of the order pH/$\mu$m and therefore,it can be safely ignored.

The quantum capacitance ($C'_{\rm Q})$ in the equivalent model represents the finite density of electronic states in a quantum wire (i.e.,CNT)^[25] and can be expressed as

$C_{\rm Q}' =N_{\rm CNT} N_{\rm Channel} C_{\rm Q0}',$

(7)

where $C'_{\rm Q0}$ $=$ 2$e^{2}/hv_{\rm F}$ $\approx$ 96.8 aF/$\mu$m. Apart from this,the inversion region capacitance ($C'_{\rm TSV})$ in Figure 4 primarily represents the equivalent oxide and depletion region capacitances^[25],$C_{\rm ox}$ and $C_{\rm dep}$,respectively. The $C_{\rm ox}$ and $C_{\rm dep}$ are mainly dependent on the radius of TSV ($r_{\rm via})$,oxide region ($r_{\rm ox})$ and depletion region ($r_{\rm dep})$ and can be expressed as

$$\begin{split} C'_{\rm TSV} {}& =\left( {\frac{1}{C_{\rm ox} }+\frac{1}{C_{\rm dep} }} \right)^{-1} \\[2mm]& =\left[{\frac{\ln \left( {{r_{\rm ox}}/{r_{\rm via} }} \right)}{2\pi \varepsilon _{\rm ox} H_{\rm TSV} }+ \frac{\ln \left( {{r_{\rm dep} }/{r_{\rm ox} }} \right)}{2\pi \varepsilon _{\rm si} H_{\rm TSV} }} \right]^{-1}. \end{split}$$

(8)

The via parasitics of SWCNT bundled TSVs are presented in Figures 5, 6 and 7 for via heights of 30,60 and 90 $\mu$m,respectively. The parasitic values are obtained using the total number of conducting channels of SWCNTs and the physical parameters of TSVs (as presented in Table 1).

3. Result and discussion

This section explains the simulation setup for the analysis of propagation delay and average power dissipation of SWCNT bundled TSVs. Using HSPICE circuit simulations,the analysis is performed for different via heights ranging from 30 to 90 $\mu$m. An input sinusoidal signal with peak voltage 2.5~V is used to analyze the delay and power dissipation. The equivalent electrical models of bundled SWCNT based TSVs are used to represent the TSV line of the DTL as shown in Figure~8. The driver resistance and driver capacitance have the following values: $R_{\rm dr}$ $=$ 292.36 $\Omega$ and $C_{\rm dr}$ $=$ 45.51 aF. The via line is terminated by a load capacitance $C_{\rm L}$ of 10 fF.

Using the DTL setup ( Figure 8) and the equivalent electrical model ( Figure 4),the propagation delay and average power dissipation are analyzed for different via heights and bundle aspect ratios. The propagation delay and power dissipation are plotted in Figures 9 and 10,respectively. It is observed that the delay and power dissipation substantially increases for higher TSV height due to an increase in $p.u.h.$ via self-resistive and capacitive parasitics as seen in Figure 5 through Figure 7. Additionally,a significant reduction in delay and power dissipation is observed for the bundle aspect ratio of 300 : 1. The primary reason behind this reduction is the via resistance and capacitance values that mainly depend on the $N_{\rm Total}$.

The quantitative value of $N_{\rm Total}$ is mainly governed by the $N_{\rm CNT}$ that depends on the bundle aspect ratio (AR). Using a fixed TSV height,the $N_{\rm CNT}$ for AR $=$ 300 : 1 is more in comparison to AR $=$ 6 : 1 that substantially reduces the via resistance with a negligible increase in via capacitance. It results in an overall reduction of delay and power dissipation.

Using a SWCNT bundled TSV with AR $=$ 300 : 1 and $H_{\rm TSV}$ $=$ 30,60 and 90 $\mu$m,the propagation delay and power dissipation are reduced by 91.3%,93.9% and 96.2%,respectively,compared to the SWCNT bundled TSV with AR $=$ 6 : 1 as summarized in Table 2. Consequently,for AR $=$ 12 : 1 and AR $=$ 60 : 1,the reductions are 44.13%,57.6%,67.5% and 11.11%,17.36%,39.1%,respectively. Based on the delay and power performance,the overall power delay product (PDP) using AR $=$ 300 : 1 is reduced by 99.58%,80.17% and 39.17% in comparison to AR $=$ 6 : 1,12 : 1 and 60 : 1,respectively (Table 3) and area delay product (ADP) using 300 : 1 is reduced by 99.99%,99.91% and 96.34% in comparison to AR $=$ 6 : 1,12 : 1 and 60 : 1,respectively (Table 4). Additionally,using Table 5,it can be inferred that the cross-sectional area significantly reduces for higher value of AR.

4. Conclusion

This paper analyzed and compared the propagation delay and power dissipation of SWCNT bundle based TSVs for different via radius. Depending on the physical configuration,a single conductor transmission line model of SWCNT bundled TSV is presented. The equivalent model is used to represent the TSV line of the DTL system. From HSPICE circuit simulations,it is observed that the delay and power dissipation of a SWCNT bundled TSV with aspect ratio of 300 : 1,60 : 1 and 12 : 1 are reduced by 91.3%,44.13% and 11.11%,respectively,compared to TSV bundle having aspect ratio of 6 : 1. Thus,SWCNT bundled TSV with higher aspect ratio is worth using as a promising filler material for future 3D ICs.