J. Semicond. > 2015, Volume 36 > Issue 6 > 065006
|

SEMICONDUCTOR INTEGRATED CIRCUITS

A high speed direct digital frequency synthesizer based on multi-channel structure

Ling Yuan, Qiang Zhang and Yin Shi

+ Author Affiliations

 Corresponding author: Ling Yuan, Email: lyuan@semi.ac.cn

DOI: 10.1088/1674-4926/36/6/065006

PDF

Abstract: This paper presents a direct digital frequency synthesizer (DDFS) for high speed application based on multi-channel structure. This DDFS has phase resolution of 32 bits and magnitude resolution of 12 bits. In order to ensure the high speed and high resolution at the same time, the multi-channel sampling technique is used and a 12 bits linear digital-to-analog converter is implemented. The chip is fabricated in TSMC 130 nm CMOS technology with active area of 0.89 × 0.98 mm2 and total power consumption of 300 mW at a single 1.2 V supply voltage. The maximum operating speed is up to 2.0 GHz at room temperature.

Key words: direct digital frequency synthesizer (DDFS), multi-channel, phase-to-sine-amplitude converters (PSAC)



[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
Fig. 1.  Conventional DDFS architecture.

DownLoad: Full-Size Img PowerPoint
Fig. 2.  DDFS based on nonlinear DAC architecture.

DownLoad: Full-Size Img PowerPoint
Fig. 3.  Architecture for the proposed multi-channel DDFS.

DownLoad: Full-Size Img PowerPoint
Fig. 4.  Simplified diagram for the DAC cell.

DownLoad: Full-Size Img PowerPoint
Fig. 5.  $Q^2$ random walk scheme.

DownLoad: Full-Size Img PowerPoint
Fig. 6.  Architecture for the PSAC.

DownLoad: Full-Size Img PowerPoint
Fig. 7.  Die photo.

DownLoad: Full-Size Img PowerPoint
Fig. 8.  Measured DDFS output spectrum. (a) SFDR: 67 dBc @ 382.5 kHz (b) SFDR: 51 dBc @ 62.1 MHz

DownLoad: Full-Size Img PowerPoint
Fig. 9.  The measured DDFS SFDR versus output frequency at clock frequency of 2.0 GHz.

DownLoad: Full-Size Img PowerPoint
DownLoad: CSV
DownLoad: CSV
DownLoad: CSV
DownLoad: CSV
DownLoad: CSV

Table 1.   Area-utilization efficiency.

DownLoad: CSV

Table 2.   Comparison between different reported DDFSS.

DownLoad: CSV
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]

    • Search

    Advanced Search >>

    GET CITATION

    shu

    Export: BibTex EndNote

    Article Metrics

    Article views: 2293 Times PDF downloads: 18 Times Cited by: 0 Times

    History

    Received: 02 November 2014 Revised: Online: Published: 01 June 2015

    Catalog

      Email This Article

      User name:
      Email:*请输入正确邮箱
      Code:*验证码错误
      Send
      Article Navigation >  Journal of Semiconductors  > 2015  >  36(6): 065006
      Ling Yuan, Qiang Zhang, Yin Shi. A high speed direct digital frequency synthesizer based on multi-channel structure[J]. Journal of Semiconductors, 2015, 36(6): 065006. doi: 10.1088/1674-4926/36/6/065006 ****L Yuan, Q Zhang, Y Shi. A high speed direct digital frequency synthesizer based on multi-channel structure[J]. J. Semicond., 2015, 36(6): 065006. doi: 10.1088/1674-4926/36/6/065006.
      Citation:
      Ling Yuan, Qiang Zhang, Yin Shi. A high speed direct digital frequency synthesizer based on multi-channel structure[J]. Journal of Semiconductors, 2015, 36(6): 065006. doi: 10.1088/1674-4926/36/6/065006 ****
      L Yuan, Q Zhang, Y Shi. A high speed direct digital frequency synthesizer based on multi-channel structure[J]. J. Semicond., 2015, 36(6): 065006. doi: 10.1088/1674-4926/36/6/065006.
      shu

      A high speed direct digital frequency synthesizer based on multi-channel structure

      DOI: 10.1088/1674-4926/36/6/065006

      • Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083, China

      More Information
      • Corresponding author: Email: lyuan@semi.ac.cn
      • Received Date: 2014-11-02
      • Accepted Date: 2014-12-07
      • Published Date: 2015-01-25

      Catalog

        Journal of Semiconductors © 2017 All Rights Reserved   京ICP备05085259号-2

        /

        DownLoad:  Full-Size Img  PowerPoint
        Return
        Return