J. Semicond. > 2016, Volume 37 > Issue 1 > 015006
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SEMICONDUCTOR INTEGRATED CIRCUITS

A low jitter supply regulated charge pump PLL with self-calibration

Min Chen1, Yuntao Liu2, Zhichao Li1, Jingbo Xiao1 and Jie Chen1,

+ Author Affiliations

 Corresponding author: Chen Jie,Email:jchen@ime.ac.cn

DOI: 10.1088/1674-4926/37/1/015006

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Abstract: This paper describes a ring oscillator based low jitter charge pump PLL with supply regulation and digital calibration. In order to combat power supply noise, a low drop output voltage regulator is implemented. The VCO gain is tunable by using the 4 bit control self-calibration technique. So that the optimal VCO gain is automatically selected and the process/temperature variation is compensated. Fabricated in the 0.13 μ m CMOS process, the PLL achieves a frequency range of 100-400 MHz and occupies a 190×200 μ m2 area. The measured RMS jitter is 5.36 ps at a 400 MHz operating frequency.

Key words: phase-locked loop, supply regulation, self-calibration, low jitter



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Fig. 1.  (Color online) Noise transfer functions.

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Fig. 2.  Block diagram of the PLL.

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Fig. 3.  Schematic of the regulator.

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Fig. 4.  (a) VCO top architecture. (b) Delay cell.

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Fig. 5.  Simulation result of VCO with 16 operating modes. (a) Highest $K_{\rm vco}$ (fast process, VDD $=$ 1.32 V, $-40$ $\du$). (b) Typical $K_{\rm vco}$ (typical process, VDD $=$ 1.2 V, 27 $\du$). (c) Lowest $K_{\rm vco}$ (slow process, VDD $=$ 1.08 V, 125 $\du$).

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Fig. 6.  Static PFD schematic.

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Fig. 7.  Charge pump schematic.

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Fig. 8.  Transient voltage $V_{\rm reg}$. (a) No voltage regulator. (b) With voltage regulator.

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Fig. 9.  (a) 100 MHz output frequency under highest $K_{\rm vco}$. (b) 400~MHz output frequency under lowest $K_{\rm vco}$.

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Fig. 10.  (Color online) microphotograph of the die.

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Fig. 11.  Measured 16 tuning curves ($V_{\rm reg}$ is precharged by Start bias).

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Fig. 12.  (Color online) Locking process of the PLL ($F_{\rm ref}$ $=$ 2 MHz, $N=$ 50).

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Fig. 13.  Measured spectrum of output signal.

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Fig. 14.  (Color online) Measured jitter histogram at 400 MHz.

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Fig. 15.  Measured RMS and peak--peak jitter.

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Table 1.   Summary and comparison with reported results.

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    Received: 06 May 2015 Revised: Online: Published: 01 January 2016

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      Article Navigation >  Journal of Semiconductors  > 2016  >  37(1): 015006
      Min Chen, Yuntao Liu, Zhichao Li, Jingbo Xiao, Jie Chen. A low jitter supply regulated charge pump PLL with self-calibration[J]. Journal of Semiconductors, 2016, 37(1): 015006. doi: 10.1088/1674-4926/37/1/015006 ****M Chen, Y T Liu, Z C Li, J B Xiao, J Chen. A low jitter supply regulated charge pump PLL with self-calibration[J]. J. Semicond., 2016, 37(1): 015006. doi: 10.1088/1674-4926/37/1/015006.
      Citation:
      Min Chen, Yuntao Liu, Zhichao Li, Jingbo Xiao, Jie Chen. A low jitter supply regulated charge pump PLL with self-calibration[J]. Journal of Semiconductors, 2016, 37(1): 015006. doi: 10.1088/1674-4926/37/1/015006 ****
      M Chen, Y T Liu, Z C Li, J B Xiao, J Chen. A low jitter supply regulated charge pump PLL with self-calibration[J]. J. Semicond., 2016, 37(1): 015006. doi: 10.1088/1674-4926/37/1/015006.
      shu

      A low jitter supply regulated charge pump PLL with self-calibration

      DOI: 10.1088/1674-4926/37/1/015006
      • 1.

        Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China

      • 2.

        College of Information and Communication Engineering, Harbin Engineering University, Harbin 150001, China

      Funds:

      Project supported by the National Key Basic Research and Development Program of China (No. 2015CB352100).

      More Information
      • Corresponding author: Chen Jie,Email:jchen@ime.ac.cn
      • Received Date: 2015-05-06
      • Accepted Date: 2015-08-20
      • Published Date: 2016-01-25

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