1. Introduction

With the development of medical electronics and portable devices, low power consumption has become one of the most important objectives for chip designers. At present, memory occupies most of the area and power consumption in a chip. The SRAM as high-performance and low-power memory is widely used in chip design. Therefore, reducing the power consumption of the SRAM can effectively prolong the equipment usage time^[1-3]. SRAM power consumption mainly comes from the static power and dynamic power consumption of the memory array, decoder, clock control module, sense amplifier, and input and output circuits. Among these, the switching power of the memory array is the largest contributor to SRAM power consumption^[4-5].

In order to reduce the switching power consumption of the memory array, the corresponding memory cell is normally opened by the word line to discharge the bit line for a short time. When the bit lines reach the correct voltage difference, the sense amplifier is turned on so as to output the corresponding data. Due to process deviation, the sense amplifier has an offset voltage^[6]. When the voltage difference in the bit lines is less than the offset voltage, it is possible to read out the error data. On the contrary, if the voltage difference is too large, it will cause additional power consumption and delay. It is important to get an accurate sense amplifier enable signal and word line pulse to achieve low power consumption in the SRAM.

The simplest clock control circuit is composed of an inverter delay chain. The chain length is adjusted by simulation. There is a shortcoming of this method: its accuracy is not high. Due to the impact of the threshold voltage, power supply voltage, and ambient temperature factors, clock control circuit, which is composed of inverter delay chain, cannot accurately track discharge time^[7]. In order to get the control signal accurately, Reference [8] puts forward the replica bit line control circuit. The replica unit of this circuit has a similar structure and environment to the memory unit in array. By controlling the replica bit line length, the circuit can better track the discharge time of the bit lines, and thus control the enable signal of the sense amplifier and the word line opening and closing.

For the sense amplifier enable signal, many different techniques have been put forth to reduce the influence on it from the threshold voltage, power supply voltage, the ambient temperature, and other factors^[9-11]. Reference [10] puts forward a digital replica bit line delay technique using multiple replica units to discharge the replica bit line. Moreover, the discharge delay time is accumulated through the delay replication circuit, which can get an accurate bit line discharge time.

Due to the adoption of a plurality of replication units, the influence of the threshold voltage deviation can be effectively reduced, so that a very accurate sense amplifier enable signal can be obtained, and the working delay and the power consumption of the SRAM can be reduced. As for the word line signal, due to the traditional replica bit line control circuit, it cannot be promptly closed after the sense amplifier enable signal is effective; thus, unnecessary power consumption is increased due to the bit line additional discharge.

Reference [12] builds an internal self-test and numerical controlled delay unit to control the word line. The self-test circuit provided a suitable input to SRAM. This ensured that SRAM could be read normally with a reduced word line opening time, thus reducing the power consumption of the memory array. However, due to the additional self-test circuit, SRAM area and power usage increased correspondingly.

In view of this, a replica bit line control circuit is proposed to optimize power for SRAM. The proposed circuit reduces the switching power of the memory array, and does not require much additional space and power.

2. Traditional replica bit line control circuit

The replica bit line control circuit is a widely used time sequence control circuit that can precisely track the delay of the bit line. The traditional capacitor ratio replica bit line control circuit is shown in Figure 1^[8]. The BS is the chip select signal, RBL is the replica bit line, RWL is the replica word line, WL is the memory array word line, GWL is the global word line, SAE is the sense amplifier enable signal, BL and BLB are the bit lines of the memory array. The basic working principle of the replica bit line control circuit is as follows:

Before the read operation starts, the bit lines of the memory array and replica bit lines are all charged to high level, and the chip select signal BS, replica word line RWL, and sense amplifier enable signal SAE are all discharged to low level. When the read cycle begins, BS is set to high level. Thus, the RWL is set to high level by charging from logic gate D1, and the RBL is discharged through replica unit under the control of the RWL. Simultaneously, the global word line GWL is set to high level. After RWL traverse logic gates B1-B4, memory array word line WL is engaged, which controls the memory cells of the array to discharge the bit line. When the line capacitance of the RBL is discharged to low level, the SAE will be set to high level through S1-S5, and the sense amplifier will be engaged to enlarge the voltage difference on the bit lines. As a result, the corresponding data is output.

The voltage difference on the bit lines $\Delta V_{\rm BL}$ can be determined by controlling the length of the replica bit line RBL, which is shown in Equation (1):

$\Delta V_{\rm BL}=V_{\rm DD}\frac{r}{h},$

(1)

where r is the length of the replica bit line, h is the height of the memory cell array, and $V_{\mathrm{DD}}$ is the power supply voltage. Because the environment of the replica cell is similar to the array storage unit, the replica bit line control circuit can accurately track the bit line discharge time, which is influenced by the threshold voltage, power supply voltage, and environment temperature.

There are two defects in the traditional control circuit of replica bit line. First, when the sense amplifier enable signal SAE is valid, the word line still needs to go through the logic gates S1 and D1 delay to shut down, which is shown in Equation (2):

$T_{\rm pulse, WL}=T_{\rm D}+T_{\rm rbl},$

(2)

where $T_{\rm rbl}$ is the replica bit line discharge time, $T_{\rm D}$ is the logic gate S1, D1 delay, $T_{\rm pulse, WL}$ is the word line opening time. The delay time $T_{\rm D}$ will increase the voltage loss, which is not necessary. Particularly, in small capacity SRAM, the loss of voltage even exceeds its own need to establish the voltage difference. In addition, the chip select signal BS needs accurate timing control, and needs to be promptly set to low when the replica bit line RBL is set to low level.

Due to the control of the replica word line RWL, the replica bit line RBL will be set to the logic state opposite to the RWL. When the BS is valid, the RBL will, in turn, act on the RWL. Thus, the RWL will be set to the same level as the RBL. As a result, when the BS is set to high for a long time, it will lead to feedback oscillations, which is shown in Figure 2, and the line capacitor of RWL and RBL will be charged and discharged continuously, giving rise to unnecessary power consumption.

3. Design of replica bit line control circuit to optimize power for SRAM

In order to overcome the shortcomings of the traditional replica bit line control circuit, we propose the following design. First, to eliminate the delay caused by the logic gates S1 and D1 in shutting off the word line, the logic gate B1 is designed to be directly controlled by the replica bit line RBL. When RBL is set to low level, the output node B1 is charged. Thus, the word line can be opened and closed in a timely manner when the sense amplifier is engaged.

Second, the charging and discharging of the RBL are all controlled by the replica word line RWL. Moreover, when the chip select signal BS is in high level, RWL is also controlled by RBL. As a result, there is a feedback oscillation between RBL and RWL. To eliminate this oscillation, the BS signal can be split into a read clock RCLK and write clock WCLK, and the logic gate B1 is added to a control signal of WCLK. Therefore, when the SRAM is undergoing a writing operation, the word line can be opened and closed by the WCLK. In addition, the anti signal of RCLK NOR the output signal of logic gate S1, and the replica word line RWL is generated. Meanwhile, the RCLK is used to control the charging operation of RBL. During SRAM read operation, RCLK is at high level; thus, the RBL charging path is turned off, avoiding feedback oscillation. Figure 3 shows the designed replica bit line control circuit to optimize power for the SRAM.

WLEN is the enable signal of word line, and the logic gate B1 is controlled by the write clock WCLK, replica bit line RBL, and replica word line RWL. When the write operation is started, WCLK can directly control the WLEN, which controls the opening and closing of the memory array word line WL. The signal timing diagram of the circuit during read cycle is shown in Figure 4.

Before the start of the read cycle, the read clock RCLK is maintained at a low level, RBL is set to high level, and RWL, WL, and SAE are all set to low level. When the read operation begins, the RCLK is set to a high level, so that the RWL is set to a high level too. As a result, the RBL is discharged by the replica unit. At the same time, the GWL is set to high level. After the delay of gates B1-B4, WL is engaged by RWL, and the bit line is discharged by the memory cell in the array.

When the replica bit line RBL is set to low level, after the delay of logic gates S1-S5, the SAE is set to high level, and then the sense amplifier is turned on. Because the logic gate B1 is controlled by the WL, the closing of RBL is no longer determined by the RWL. After the RBL is set to low level, the word line can be closed after the delay of logic gates B1-B4, eliminating the delay effect caused by the logic gates S1 and D1. Thus, as shown in Equation (2), the word line opening time $T_{\rm WL, pulse}$ is equal to the replica bit line discharging time $T_{\rm rbl}$ without the effect of delay $T_{\rm D}$ . By adjusting the size of the devices to equalize the delay of logic gates S1-S5 and B1-B4, the word line can be turned off in time to avoid unnecessary power loss.

In order to verify that the SRAM works normally and saves memory array switching power consumption with the designed replica bit line control circuit, a 256 × 8 SRAM is proposed and designed based on the architecture suggested in References [13-15]. Its structure is shown in Figure 4. The storage unit of memory array uses the traditional 6T storage structure, due to the capacity of designed SRAM being 2-kb, so it does not need to split the memory array block.

The replica bit line control circuit to optimize the power consumption for the SRAM is placed on the left side of the memory array. The replica unit is close to the memory array, which can better track the influence from the threshold voltage, power supply voltage, and ambient temperature variables, thus reducing the SRAM read delay and power consumption. The load unit and drive unit of the replica bit line circuit structure are shown in the dashed box of Figure 5, and their basic structure is similar to the 6T storage structure. Among them, the Q node of the load unit and the node QB of the driving unit are all connected to VDD, so the discharge of the replica bit line will be influenced by the leakage current between node Q and RBL, which can effectively adapt to the slowest discharge situation caused by the leakage current of the bit line.

The decoder circuit and the address latch circuit are all placed on the left of the replica bit line control circuit. Close to the memory array, the word line length can be shortened. As a result, the switching power loss caused by the word line discharge is reduced.

In addition, all circuits except the memory array are needed to be clock controlled. Therefore, the clock circuit module is also arranged below the decoding module, and the left and right sides are the address latch module and the replica bit line control circuit, respectively.

4. Experimental results and performance comparison

The replica bit line control circuit and whole SRAM are designed in SMIC 65-nm CMOS process, and the layout is shown in Figure 6. The layout area is 108.7 × 53.94 μm². The experimental results show that the maximum working frequency at 1.2-V supply voltage is 1.25 GHz, and its corresponding power is 7.1 mW. When the supply voltage changes to 0.7 V, the maximum working frequency is 220 MHz, and its corresponding power is 575.1 μW.

The designed replica bit line control circuit and traditional replica bit line control circuit are applied to the design of SRAM circuit respectively, and they have been compared in a variety of PVT (process corner, voltage, temperature) combinations. The results are listed in Table 1. PVT represents the process corner, power supply voltage, and the ambient temperature change in the circuit manufacturing and in normal operation of the circuit.

Among these, the process corners consist of five typical cases, which are shown as follows: TT (typical NMOS and typical PMOS); FF (fast NMOS and fast PMOS); SS (slow NMOS and slow PMOS); SF (slow NMOS and fast PMOS); FS (fast NMOS and slow PMOS).

Here, $\Delta V$ and $\Delta V_{\rm max}$ represent the bit line swing when the sense amplifier starts working and the word line shut off, respectively. When the sense amplifier starts working, traditional replica bit line control circuit needs to effectively shut down the word line after the delay of an inverter and a NOR gate. The voltage loss can be obtained from Table 1, which shows that voltage loss even exceeds the voltage difference needed by the sense amplifier, thus causing unnecessary switching power.

Switching power $P_{\rm sw}$ is obtained from the power required to charge the node, which is shown in Equation (3)^[5]:

$P_{\mbox{sw}} =\alpha f C_{\mbox{L}} V_{\mbox{DD}} \Delta V ,$

(3)

where $\alpha$ is the switch activity, f is the circuit working frequency, $C_{\rm L}$ for load capacitance, $V_{\mathrm{DD}}$ is the supply voltage, and $\Delta V$ is the charge and discharge amplitude of the node. In the case of the same power supply voltage, operating frequency, switching activity, and load capacitance, the switching power consumption of the array is determined by the difference between the maximum bit line swings. In this paper, we proposed a new replica bit line control circuit to overcome the shortcomings of traditional replica bit line control circuit. As we discussed before, due to the effect of logic gate S1 and D1 in Figure 1, the word line pulse of the traditional replica circuit is longer than the pulse of sense amplifier signal, which will discharge the voltage of bit lines more than we need. To resolve this problem, the logic gate B1 is designed to be directly controlled by the replica bit line RBL. When RBL is set to low level, the output node B1 is charged. As a result, the word line can be promptly closed by tracking the sense amplifier enable signal, which greatly reduces the voltage loss. For a 2-kb SRAM, 53.7% of the memory array switching power consumption can be saved under 1.20-V power supply.

5. Conclusion

In this paper, based on the analysis of the traditional replica bit line control circuit, a new type of SRAM power control circuit is proposed. Through balancing word line opening, shutdown path delay, and chip select signal decomposition method, the word line can be timely shut off. The feedback oscillation between the replica bit line and the replica word line is effectively avoided. As a result, switching power losses caused by the bit line unnecessary discharge is successfully reduced. In order to verify the designed replica bit line control circuit for saving power consumption, a 2-Kb SRAM is fully custom designed in SMIC 65-nm CMOS process, and compared with the traditional replica bit line control circuit. Under different process corners, the results show that the designed circuit can effectively control the time sequence of SRAM and reduce the switching power consumption of the memory array.