Fig. 1.
Block diagram of the proposed ADC and its timing diagram.
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| Citation: |
Yi Shen, Shubin Liu, Zhangming Zhu. A 10 b 50 MS/s two-stage pipelined SAR ADC in 180 nm CMOS[J]. Journal of Semiconductors, 2016, 37(6): 065001. doi: 10.1088/1674-4926/37/6/065001
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Y Shen, S B Liu, Z M Zhu. A 10 b 50 MS/s two-stage pipelined SAR ADC in 180 nm CMOS[J]. J. Semicond., 2016, 37(6): 065001. doi: 10.1088/1674-4926/37/6/065001.
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A 10 b 50 MS/s two-stage pipelined SAR ADC in 180 nm CMOS
DOI: 10.1088/1674-4926/37/6/065001
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Abstract
A 10-bit 50 MS/s pipelined SAR ADC is presented which pipelines a 5-bit SAR-based MDAC with a 6-bit SAR ADC. The 1-bit redundancy relaxes the requirement for the sub-ADC decision in accuracy. The SAR-based and "half-gain" MDAC reduce the power consumption and core area. The dynamic comparator and SAR control logic are applied to reduce power consumption. Implemented in 180 nm CMOS, the fabricated ADC achieves 56.04 dB SNDR and 5mW power consumption from 1.8 V power supply at 50 MS/s. -
References
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