1. Introduction
As the scaling of planer complementary metal oxide semiconductor (CMOS) technology enters the sub-10 nm era,the silicon based industry is facing many problems such as short channel effects. It will reach its fundamental scaling limits by 2018 as per the International Technology Roadmap for Semiconductors (ITRS) roadmap[1]. Various nanoscale devices have gained attention in recent years as a replacement of CMOS technology in the sub-10 nm era. The carbon nanotube field effect transistor (CNTFET) is one of the promising devices among them. The carbon nanotube (CNT) exhibits ideal electronic and mechanical properties. CNT diameters can be up to 1 nm small and a near ballistic transport mechanism can be assumed for small channel length (~ 200 nm)[2]. CNTFET seems a very attractive solution to the silicon based industry due to the similar device structure of the conventional Metal oxide semiconductor field effect transistor (MOSFET),hence the CMOS device infrastructure can be reused[3]. That is why both p-type and n-type CNTFETs have been successfully fabricated recently[4, 5, 6].
A great deal of work is going on the modelling and simulation of CNTFET,but the device physics and transport mechanism of CNTFET are yet to be explored. There are two main approaches towards modelling: the non equilibrium Green function (NEGF) approach[7] and the ballistic transport mechanism approach[8]. The NEGF approach consists of self consistent equations which need complex calculations and hence are very time consuming. The problem with this approach is that it cannot be used for circuit simulations. The second ballistic transport mechanism approach is simple for modelling the I-V and C-V characteristics. The model used is based on the latter approach. In this approach,modelling is based on the principle of calculation of the CNT charge,which is responsible for the transport mechanism. The CNT potential is responsible for the charge developed on the CNT surface and that charge is responsible for current flow. Also CNT surface potential will alter the band of the channel.
The model directly relates the transport mechanism with chirality. Our model is valid for zigzag (n,0) CNTs for variable diameters and channel lengths. The model is valid as long as the CNT behaves as semiconducting. Necessary approximations are made for the calculations. The beauty of the model is it can be used in any conventional circuit simulator like HSPICE as it denies self consistent equations. The model is simulated in MATLAB for I-V characteristics. The simulations are compared with that of NanoTCAD ViDES[7] for the same device parameters and are found to be in the same trend. For circuit simulations,the model is converted to HSPICE model file using Verilog-A and look up tables are formed with that of NanoTCAD ViDES simulations data. Lastly,circuit simulations are done for the inverter and SRAM.
2. Modeling theory
Due to one dimensional band structure of CNTFET,the transport inside CNTs can be assumed to be near ballistic. For ballistic transport the current is independent of the CNT length for wide ranges[9]. The reported mean free path for CNT is ~ 200 nm[10]. Hence channel length is not a dominant factor for current calculations. The dominant factor is chirality or in other words diameter,as it directly affects the bandgap,threshold voltage and carrier concentration. Another important factor that affects current calculations is oxide capacitance,which consists of oxide thickness and its dielectric constant value. The charge base model used in this work is shown in Figure 1[8]. There will be induced potential developed across the CNT and oxide interface due to the action of applied gate voltage. It shows the effect of CNT surface potential (ψcnt) on the band diagram of the channel. The band will get shifted by an amount of ψcnt in the downward direction on applying positive gate bias and vice versa. In CNTFET,the ON current ((ION) is limited by the amount of charge induced on the channel by gate voltage,but not on doping of CNT at source and drain sides. However,the OFF current (IOFF) is affected by doping as tunnelling depends on the band profile of source and drain.
The model is developed and applied to the top gate structure of CNTFET as shown in Figure 2. The device is of the conventional type as doping is introduced at source and drain sides. The back gate (body) is at zero bias and all the potentials are taken with respect to the body (substrate). The role of doping is shifting of the Fermi level of the source and drain sides,as a result of which conduction takes place. The doping value used is 5 × 103 as a molar fraction,which is defined as the ratio between the number of doping atoms over the number of atoms[11].
The CNT is defined by the chiral numbers (n,m) which are responsible for its properties. The basic parameters like diameter (d) and bandgap ( $E_{\rm g}$ ) are calculated with the help of (n,m). The first and most important step is to calculate d of the nanotube,which is given by[12]:
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$ d=\frac{\sqrt 3 a}{\pi }\sqrt {n^{2} + m^{2}+2 nm}, $ |
(1) |
where a is the inter-atomic distance between carbon atoms and its value is 0.142 nm[12]. The next important step is the conduction band minima calculation,which can be done using the bandgap. Conduction band minima for the CNT are the base for all the calculations as the limit for integrations. It can be defined that the conduction band minima for the first subband can be set to half of the bandgap at no gate bias. The value of bandgap is dependent on diameter and given as[13]:
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$ {{E}_{\text{g}}}=\frac{2a{{V}_{\text{pp}\pi }}}{\sqrt{3}d}, $ |
(2) |
where $V_{\rm pp\uppi }$ is the carbon π-π bond energy and its value is 3.033 eV[12]. The transport mechanism is directly dependent on the intrinsic charge carrier concentration ( $n_{\rm CNT}$ ) of the nanotube which can be written as[14]:
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$ n_{\rm cnt} =\int^\infty_{E_{\rm C}}{D\left(E\right)f\left(E\right){\rm d}E}, $ |
(3) |
where D(E) is density of states and f(E) is Fermi-Dirac distribution. The values of D(E) and f(E) are given by Equations (4) and (5) as:
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$ f\left(E \right)=\frac{1}{1+{\rm exp} \frac{E-E_{\rm F}}{kT}}, $ |
(4) |
where k is the Boltzmann constant,T is the operating temperature and EF is the Fermi level of the CNT.
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$ D\left( E \right)\text{d}E=2\sum\nolimits_{1}^{\text{All}\text{bands}}{\frac{4}{\pi {{V}_{\text{p}{{\text{p}}_{\pi }}}}a\sqrt{3}}\frac{E}{\sqrt{{{E}^{2}}-{{E}_{\text{C}}}}}\text{d}E}, $ |
(5) |
where $E_{\rm C}$ is the conduction band energy. The density of states is calculated for the first subband only as the contribution of next level subbands is negligible. Combining Equations (4) and (5),we can rewrite Equation (3) as:
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$ {{n}_{\text{cnt}}}={{N}_{\text{c}}}I\text{exp}\left( \frac{-{{E}_{\text{c}}}}{kT} \right), $ |
(6) |
where
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$ {{N}_{\text{c}}}=\frac{8kT}{\pi {{V}_{\text{p}{{\text{p}}_{\pi }}}}a\sqrt{3}}, $ |
(7) |
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$ I=\frac{1}{\sqrt {kT}}\int_0^\frac{6E_{\rm C}}{T} {\frac{\left( kTx+E_{\rm C} \right)}{\sqrt {x\left( kTx+2E_{\rm C} \right)} }{\rm exp}\left(-x \right){\rm d}x}. $ |
(8) |
The analytical calculation for I is given in Reference [15]. The source and drain side Fermi levels are at zero for intrinsic CNT. By introducing doping,the CNT can be n-type or p-type and it directly affects the nature of CNTFET and its current value. If $\upDelta E_{\rm F}$ is the shift in Fermi level due to doping then the value of $\upDelta E_{\rm F}$ is given as[14]:
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$ \Delta {E_{\rm{F}}} = kT{\rm{ln}}\left( {1 + \frac{N}{{{n_{{\rm{cnt}},{\rm{i}}}}}}} \right), $ |
(9) |
where N is the doping concentration. The value of $\upDelta E_{\rm F}$ is positive for n-type and negative for p-type doping. Let $V_{\rm SS}$ and $V_{\rm DS}$ be the source to substrate and drain to substrate bias respectively then the drain current $I_{\rm DS}$ can be calculated using the Launder Equation [16] as:
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$ IDS=qkTπh{ln[1+eΔEF+q(Ψcnt(0)−VSS−ϕ0)−ECKT]−ln[1+eΔEF+q(Ψcnt(L)−VDS−ϕ0)−ECKT]},
$
|
(10) |
where q is the electronic charge and h is Planck's constant. $\Psi_{\rm cnt}$ and $\phi_{0}$ are the CNT surface potential due to the front gate and back gate (substrate) respectively. For the top gate device structure, $\phi_{0}$ is set to zero. The value of $\Psi_{\rm cnt}$ is different at the source and drain and can be calculated as[15]:
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$ \Psi_{\rm cnt} (0) = V_{\rm GS}-V_{\rm fb}, $ |
(11) |
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$ Ψcnt(L)=VGS−δIe−1−Vfb+δm(Vcb+ϕ0+Ec−ΔEF−KTq)1+δm,
$
|
(12) |
where $V_{\rm GS}$ is the gate to body bias, $V_{\rm cb}$ is the induced potential between the carbon nanotube and the substrate due to the drain and source terminal voltages and $V_{\rm fb}$ is flat band voltage. Since the calculations of $I_{\rm DS}$ and $\Psi_{\rm cnt}$ consist of $E_{\rm C}$ which depends on chirality,hence our model directly relates the current transport with chirality. The values of m and δ[15] for channel length (L) are given by:
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$ m=\frac{\sqrt {\frac{2E_{\rm C}}{kT}+1}-Ie^{-1}}{\frac{2KT}{q}}, $ |
(13) |
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$ \delta =\frac{qLN_{\rm C}}{C}. $ |
(14) |
Figure 3 shows the quantum capacitance model for 1-D transport. It can be seen that the total capacitance (C) is the series combination of oxide capacitance ( $C_{\rm ox}$ ) and quantum capacitance ( $C_{\rm q}$ ),which can be calculated as:
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$ C=\frac{{C_{\rm q}C}_{\rm ox}}{C_{\rm ox}+C_{\rm q}}. $ |
(15) |
If $t_{\rm ox}$ is the thickness of oxide material, $\varepsilon_{0}$ is the dielectric constant for the material used and r is the radius of the nanotube,then the value of oxide capacitance ( $C_{\rm ox}$ ) is given as[17]:
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$ C_{\rm ox}=\frac{2\pi \varepsilon_{0}L}{{\rm ln} \frac{t_{\rm ox}+r+\sqrt {t_{\rm ox}^{2}+2t_{\rm ox}r}}{r}}. $ |
(16) |
The value of quantum capacitance can be calculated as[18]:
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$ C_{q}=\frac{\partial q_{\rm cnt}}{\partial \Psi_{\rm cnt}}, $ |
(17) |
where $q_{\rm cnt}$ is the charge developed across the CNT channel due to $V_{\rm GS}$ and value is given as[19]:
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$ q_{\rm cnt}=\frac{q}{2}n_{\rm cnt}{\rm exp} {\left( \frac{\Psi_{\rm cnt}}{kT} \right)\left[1+{\rm exp} \left( \frac{-V_{\rm DS}}{kT} \right)\right]}. $ |
(18) |
From Equations (11) and (12),the $\Psi_{\rm cnt}$ - $V_{\rm GS}$ characteristics are plotted and are drawn in Figure 4. It has been observed that $\Psi_{\rm cnt}$ follows $V_{\rm GS},$ for $V_{\rm GS}$ value less than the first conduction band minima. The first conduction band minima can be calculated as 0.45/d. The $\Psi_{\rm cnt}$ - $V_{\rm GS}$ characteristics are plotted for three different diameters and it can be inferred from the results that the characteristics follow the same trend. With the necessary approximations,the I-V characteristics are calculated using the above model equations for top gate CNTFET structure. The $I_{\rm DS}$ - $V_{\rm DS}$ and $I_{\rm DS}$ - $V_{\rm GS}$ characteristics obtained with MATLAB simulations through the model and simulations done in NanoTCAD ViDES are shown in Figures 5(a) and 5(b) respectively. Device parameters used for all simulations are provided in Table 1.The simulations based on the model have to be found in the same trend represented by the corresponding characteristics obtained with NanoTCAD ViDES simulations. However,the little deviation can be attributed to the different modelling approaches followed. NanoTCAD~ViDES~is a device simulator able to compute transport in nanoscale devices,solving self-consistently the 3D Poisson and quantum transport equation within the NEGF formalism[7]. On the other hand,the model used is CNT charge based,which is responsible for CNT potential and band shift.
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For further analysis,simulations are done for different parameters that affect the performance of the device,namely the chirality (diameter) and oxide thickness. It is clear from the simulations that as we increase the diameter of nanotube,current increases as shown in Figure 6(a). It is due to the reason that more charge carriers develop inside the nanotube for the same gate voltage,which is responsible for conduction. As the bandgap is inversely proportional to the diameter,hence the larger the diameter the smaller the bandgap,it would result in late saturation. Similar simulations for various oxide thicknesses are shown in Figure 6(b). The curves follow the normal trend i.e. current increases as oxide thickness decreases; this is due to the large oxide capacitance for low oxide thickness. Also the large gate capacitance is responsible for good control over gate bias.
3. Circuit simulations
Once the model is developed and simulated in MATLAB for the I-V characteristics,the model can be used for circuit simulations if there are no self consistent equations. If there is any self consistent equation,then it has to be written in simple manner with some constants,like the relation of $\Psi_{\rm cnt}$ with $V_{\rm GS}$ finds a self consistent solution. In order to reduce the computational complexity the relation must be simplified. The well known relation is given by[20]:
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$ {\Psi _{{\rm{cnt}}}} = {V_{{\rm{GS}}}} - \alpha ({V_{{\rm{GS}}}} - {\Delta _1}), $ |
(19) |
where $\upDelta _{1}$ is the first conduction band minima and $\alpha = \alpha + \alpha_{1}V_{\rm DS} + \alpha_{2} (V_{\rm DS})^{2}$ . The value of $\alpha $ can be calculated by plotting $V_{\rm GS}$ with $\Psi_{\rm cnt}$ . The value of $\alpha $ depends on d and $t_{\rm ox}$ . The problem for this approach is that if we change the chirality or diameter then the value of $\alpha $ changes. As is clear from Equations (11) and (12) in our model the relation of $\Psi_{\rm cnt}$ with $V_{\rm GS}$ finds a direct relation with the basic parameters. By using the mentioned equation,we developed the HSPICE model and simulated voltage transfer characteristics (VTC) for the inverter and compared them with NanoTCAD simulations data in the form of a lookup table (Figure 7).
The difference in the two VTCs is due to the fact that CNTs are by default p-type in nature[21]. So p-type CNTFET tends to remain in the linear region for a longer time than n-type,which results in the characteristics corresponding to NanoTCAD ViDES simulations. The VTC for NanoTCAD ViDES simulations has been plotted in HSPICE using the lookup table method.The same device is used to design the 6T SRAM,which consists of two cross coupled inverters and two pass transistors. Figure 8 shows SRAM cell structure using CMOS and CNTFET. The performance of the SRAM cell is analysed by measuring the important Figure of Merit called static noise margin (SNM). SNM is defined as the maximum voltage amplitude of external signal that can be algebraically added to the noise-free worst-case input level without causing the output voltage to diverge from the allowable logic voltage level[22]. Recent research shows that CNT based SRAM shows improvement in all performance parameters over conventional CMOS based design[23]. It is due to the reason that SNM depends on the threshold voltage of the PFET and NFET. In CNTFET,the threshold voltage depends on the chirality instead of the cell ratio,which can be used to design a novel SRAM cell[24]. The simplest method to measure the SNM is by plotting a butterfly curve,which results from the VTC of the two inverters. The VTC of one inverter is plotted with the inverse VTC of the second inverter to obtain the butterfly curve as shown in Figure 9. SNM can be calculated by measuring the side of the longest square that can be fitted between the mirrored butterfly curve. The standby SNM is dependent on the VTC of the cross couple inverters. The standby operation is defined when the cell tends to retain the data value as long as the SRAM cell is supplied by $V_{\rm dd}$ . The SNM values are 0.4 V for our model SRAM cell and 0.3 V for Nano TCAD simulations. This shows the considerable improvement of our model for circuit application.
4. Conclusion
A novel analytical model is presented which relates the transport mechanism directly with the chirality. The model is based on CNT surface charge calculation from the chirality and gate bias. The model is simple and can be used for circuit simulations as it denies the self consistent equations. The model is applied to the top gate CNTFET structure and compared with simulations from NanoTCAD ViDES. The model can be easily extended to Double gate geometry under the quantum capacitance limit. The HSPICE model is developed using Verilog-A and circuit simulations are performed for inverter and SRAM. The model shows considerable improvement in SNM for SRAM over NanoTCAD ViDES simulations data.
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