Impact of underlap spacer region variation on electrostatic and analog performance of symmetrical high-<i>k</i> SOI FinFET at 20 nm channel length

Neeraj Jain; Balwinder Raj

doi:10.1088/1674-4926/38/12/122002

J. Semicond. > 2017, Volume 38 > Issue 12 > 122002

SEMICONDUCTOR PHYSICS

Impact of underlap spacer region variation on electrostatic and analog performance of symmetrical high-k SOI FinFET at 20 nm channel length

Neeraj Jain and Balwinder Raj

+ Author Affiliations

Corresponding author: Neeraj Jain, E-mail: erneerajjain@gmail.com, balwinderraj@gmail.com

DOI: 10.1088/1674-4926/38/12/122002

Abstract: Continued scaling of CMOS technology to achieve high performance and low power consumption of semiconductor devices in the complex integrated circuits faces the degradation in terms of electrostatic integrity, short channel effects (SCEs), leakage currents, device variability and reliability etc. Nowadays, multigate structure has become the promising candidate to overcome these problems. SOI FinFET is one of the best multigate structures that has gained importance in all electronic design automation (EDA) industries due to its improved short channel effects (SCEs), because of its more effective gate-controlling capabilities. In this paper, our aim is to explore the sensitivity of underlap spacer region variation on the performance of SOI FinFET at 20 nm channel length. Electric field modulation is analyzed with spacer length variation and electrostatic performance is evaluated in terms of performance parameter like electron mobility, electric field, electric potential, sub-threshold slope (SS), ON current (I_on), OFF current (I_off) and I_on/I_off ratio. The potential benefits of SOI FinFET at drain-to-source voltage, V_DS = 0.05 V and V_DS = 0.7 V towards analog and RF design is also evaluated in terms of intrinsic gain (A_V), output conductance (g_d), trans-conductance (g_m), gate capacitance (C_gg), and cut-off frequency (f_T = g_m/2πC_gg) with spacer region variations.

Key words: SOI FinFET, SCEs, underlap region, DIBL, analog and RF performance

1. Introduction

As the technology is shrinking down, the transistor leads to achieving low power and high performance devices in semiconductor industries. The gate loses the control of current flow and potential distribution in the channel region, which significantly increases the undesirable effects known as SCEs. The downscaling of the semiconductor device improves the chip functionality and speed of device in terms of frequency. To mitigate these short channel effects to some extent, multigate structures have become popular in chip industries. Due to improvement in technology at each generation node, chip industries migrate from geometric scaling to the equivalent scaling which significantly enhances the performance by adding the non-digital functionality called analog/RF implementation in the circuit design. For analog and RF applications, the performance of scaled MOSFETs degraded at lower technology nodes. Multigate structures provide high performance by improving the SCEs which enhance the value of drain current, fast switching and less leakage current^[1].

With the invention of FinFET (multigate structure) came revolutionary change in the complex integrated circuits due to its 3-D (dimensional) quasi planar geometry^[2]. FinFET is a most desirable structure in complementary metal oxide semiconductor (CMOS) technology due to its excellent scalability, easy fabrication steps and it is very close to MOSFET in respect to layout^[3]. Therefore world semiconductor leading companies like TSMC and Intel manufactured the FinFET at 16 and 22 nm technology nodes respectively and others are further trying to improve the SCEs of FinFET structures by optimizing the gate–source/drain high-k underlap region at lower technology nodes^{[4, 5]}. However, tradeoff always occurs among SCEs, analog and RF performance parameters^[6–8]. Further improvement in underlap FinFET can be done with high-k (k = 22) spacer region variation and source/drain engineering techniques^{[9, 10]} by analyzing the electric field, electrostatic potential and electron mobility modulation in the underlap and channel region of FinFET structure.

A lot of advanced device structures like pi-gate^[11], ohm-gate^[12], tri-gate, planar double gate SOI MOSFETs^[13], bulk FinFETs, SOI FinFETs and all around gate^[14–19] have been proposed and lot of work has been done with high-k and dual-k spacer to improve the SCEs and performance of underlap FinFET for analog and RF design^[20]. High-k spacer is used to improve the performance of underlap FinFET by improving the I_on (on-current) and lowering the barrier in undoped spacer regions^[21]. However high-k spacers slightly degrade the performance of the device in terms of outer parasitic fringing capacitance.

Silicon-on insulator (SOI) technology is well suited for analog and RF circuit design due to its isolation and high frequency functionality with reduction of SCEs, reduced drain induced barrier lowering (DIBL) and excellent scalability performance^[22–24]. With the downscaling of planar transistor below 32 nm technology, high-channel doping is required to control the SCEs and CMOS transistors suffer by mobility degradation, high-threshold voltage variation and increased leakage power consumption. So, SOI FinFET becomes the viable alternative choice in sub nanometer technology without heavily doped channel and improves the performance of CMOS family with improved carrier mobility and excellent controlling property of channel region. However, SOI FinFET suffers by resistive and capacitive parasitic effect which causes the degradation of drive current and speed of device at lower technology node. This high parasitic resistance generated due to need of thin fin for better controlling of channel and parasitic capacitance arises due to gate-to-drain, gate-to-source coupling and proximity of fin-to-fin spacing^[25]. Significant work has been done by various researchers to analyze the electrostatic and transport properties inside the SOI FinFET^[25–28]. The extension of source/drain region significantly reduces the parasitic resistance and improves the drive current of FinFET device^[29–32]. Further for high-performance analog design, underlap spacer region is used for optimization purpose^[33–35]. Previously reported underlap FinFETs have already been designed with high-k and dual-k spacer engineering techniques to achieve good control of short channel effects (SCEs)^{[20, 36]}. However the main issues of underlap FinFETs are increased underlap resistance and controlling of doping profile. This issue however is improved by high-k spacers in the underlap region in^[21] with compromising in outer parasitic fringing capacitance. Similarly Pal et al.^{[5, 37]} demonstrate the symmetrical and asymmetric dual-k spacers in underlap region to improve the SCEs and enhance the performance of FinFET device. Goel et al.^[38] proposed the asymmetrical dual-k spacer in underlap region at the drain side for low power and digital SRAM applications. Thus performance of FinFET deeply depends upon the process variation parameters and underlap spacer region and oxide thickness etc. This work explores the high-k spacer symmetrical SOI FinFET structure with extended source/drain region and performance of FinFET is explored by variation of high-k underlap spacer region. Sensitivity of spacer region on the performance of FinFET evaluated at V_DS = 0.05 V and V_DS = 0.7 V in terms of performance parameters like I_on, I_off, I_on/I_off ratio, trans-conductance (g_m), output conductance (g_d), intrinsic gain (A_V), gate capacitance (C_gg) and cut-off frequency (f_T). Physical insight into the SOI FinFET is explored with the help of electric field modulation, variation and analysis of mobility in the spacer region. This gives an opportunity for a designer to design SOI FinFET with optimum value of high-k spacer in analog/RF circuits.

In this paper 3D simulations of high-k spacer symmetrical SOI FinFET have been carried out to explore the electrostatic, analog and RF figures of merit at 20 nm channel length. Further optimization of FinFET is done with spacer length variation to obtain the optimum performance. Starting with the introduction Section 2 includes the symmetrical SOI FinFET device structure along with all dimensions, doping concentration, materials and models used in the 3-D simulation process. Section 3 describes the electrostatic, device scalability, analog and RF performance exploration of SOI FinFET. Finally, the conclusion is given in Section 4.

2. Device structure and simulation methodology

Schematic structure and cross section view of high-k spacer symmetrical SOI FinFET structure are shown in Figs. 1(a) and 1(b) respectively. In SOI FinFET structure, 20 nm channel length is considered for 3-D simulations. Source/drain of SOI FinFET is heavily doped as n-type 1 × 10²⁰ cm⁻³ and channel of structure is lightly doped as p-type 1 × 10¹⁵ cm⁻³. Source/drain is heavily doped to overcome the effect of mobility degradation which is generated due to Coulomb scattering. Here the total effective width of SOI FinFET transistor $W = \left( {2{H_{\rm Fin}} + {W_{\rm Fin}}} \right)$ is considered because the total current of FinFET structure is the effect of all current components flowing along sidewalls and top surface of Fin^[39]. The structure parameters of SOI FinFET device used for 3D simulation in this paper are given in Table 1. Fig. 1(b) shows the cross section view of high-k spacer symmetrical SOI FinFET structure in which high-k spacer is used for underlap region at the source/drain side. The high-k spacer is used to increase the I_on current of device by optimizing the gate-induced barrier lowering (GIBL). A substrate with lightly doped concentration 1 × 10¹⁵ cm⁻³ is used to minimize the effect of random dopants fluctuations in SOI FinFET for performances analysis^[40].

Figure 1. (Color online) (a) Symmetrical high-k spacer SOI FinFET (Device-D1). (b) Cross-section view of Device-D1.

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Table 1. Dimensional values used for simulation in this paper.

Parameter	Description	Device-D1
W_Fin	Fin width	10 nm
H_Fin	Fin height	26 nm
L_g	Gate channel length	20 nm
t_ox	Oxide thickness	0.9 nm
BOX	Thickness of buried oxide	40 nm
L_{sp, hk}	High-k (HfO₂, k = 22) spacer length under source/drain side	2–16 nm
W_s/d	Source/drain width	40 nm

DownLoad: CSV | Show Table

The 3-D simulations of high-k spacer symmetrical SOI FinFET structure are carried out using Sentaurus TCAD simulator tool^[41] and threshold voltage (V_th) of SOI FinFET is set 0.2 V for the fixed value of drain–source voltage (V_DS = 0.7 V) by optimizing the gate metal work function (Φ_m). The equivalent oxide thickness (t_ox) is given a value of 0.9 nm^[42–44] with supply voltage V_DD of 0.7 V and other parameters considered according to International Technology Roadmap for Semiconductors^[45]. The simulation validation of simulator is investigated by reported results in the previous literature data of Ref. [44]. SOI FinFET device is further explored for the analog and RF performance parameters like on-current (I_on), off-current (I_off), trans-conductance (g_m), output conductance (g_d), intrinsic gain (A_v), total gate capacitance (C_gg) and device cut-off frequency (f_T) with consideration of electrostatic analysis. The models considered in this paper are quantization model, velocity saturation model, concentration-dependent and field-dependent mobility model for doping process^[46]. The inversion mobility Lombardi CVT^[47] and models of auger recombination with Shockley–Read–Hall (SRH)^[47–49] are also effectively used in simulation process. For numerical simulation carrier transport model, junctions with smooth meshing and all biasing is done at room temperature and performance of high-k SOI FinFET evaluated for high and low value of drain– source voltages V_DS = 0.7 V and V_DS = 0.05 V respectively .

3. Performance exploration of SOI FinFET

3.1 Electrostatic performance

The electric field (E_x) along the channel length, electric field (E_z) along the channel width and total effective field (E) at different values of high-k spacer length along the channel position (towards x-axis, from source to drain, left to right) of symmetrical SOI FinFET at V_DS = 0.05 V and V_DS = 0.7 V are shown in Figs. 2(a), 2(b), Figs. 3(a), 3(b) and Figs. 4(a), 4(b) respectively. The device D1 (high-k SOI FinFET) placed with x, y, z coordinate at 1, 1, 1 μm location with source end and all electrostatic parameters are simulated and performance is explored between 30 to 92 nm region along the device length. This 30 to 92 nm region includes the effective channel of SOI FinFET.

As we can analyze from the simulated results shown in Figs. 2(a) and 2(b), more inversion charge accumulated near the gate electrode surface at V_DS = 0.05 V compared to V_DS = 0.7 V due to more control of the gate terminal. At V_DS = 0.7 V, the field shifted towards the drain end due to more effect of drain potential, and controlling of gate electrode on accumulation of charge in the channel near the gate surface reduces. At V_DS = 0.05 V the effect of spacer length variation can be analyzed by field peak value at the source end. At 2 nm, the spacer field peak at source end is low due to less charge accumulation in the spacer region and increases significantly at 5 nm spacer length. More charge accumulated and distributed on increasing the spacer length and electric field peak drops significantly. Simultaneously, number of peaks increases on increasing the spacer length due to more distribution of charge and drain current decreases significantly. At V_DS = 0.7 V, field shifted towards drain end and peaks drop on increasing the spacer region. At 2 nm value of spacer length, parallel electric field (E_x) along the channel is high and a high value of drain current is generated. At 16 nm value of spacer length, the strength of electric field reduces and effective current value decreases.

Figure 2. (Color online) Simulated results of SOI FinFET along the channel position (source to drain, left to right) at different spacer length for electric field, E_x component at (a) V_DS = 0.05 V, (b) V_DS = 0.7 V.

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As the simulated result shows in Figs. 3(a) and 3(b), the electric field along the width of channel shows multiple peaks of electric field in the channel region both at V_DS = 0.05 V and V_DS = 0.7 V respectively. At low value of V_DS = 0.05 V and low value of spacer 2 nm the fields shows almost symmetrical nature and increasing the spacer length more multiple peaks of field generated and it lost its symmetrical nature as shown in Fig. 3(b). At V_DS = 0.7 V the field is focused towards the drain end.

The effective field is more due to gate bias compared to drain bias at low value of V_DS = 0.05 V and at low value of spacer length 5 nm. The field is low at 2 nm spacer then increases significantly at 5 nm spacer, then it distributed towards the channel length due to drain bias as shown in Fig. 4(a). At V_DS = 0.7 V fields are more distributed toward the channel length as shown in Fig. 4(b). So, at high value of V_DS = 0.7 V and low spacer value of 2 nm, the high value of effective field (E_z) generated and due to high field and large peak value at low spacer value, on-current (I_on) of SOI FinFET increases compared to the on-current (I_on) at high spacer value of 16 nm.

Figure 3. (Color online) Simulated results of SOI FinFET along the channel position (source to drain, left to right) at different spacer length for electric field, E_Z component at (a) V_DS = 0.05 V, (b) V_DS = 0.7 V.

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Figure 4. (Color online) Simulated results of SOI FinFET along the channel position (source to drain, left to right) at different spacer length for total effective electric field, component at (a) V_DS = 0.05 V, (b) V_DS = 0.7 V.

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The electrostatic potential and electron mobility along the channel position of SOI FinFET for different values of spacer length at V_DS = 0.05 V and V_DS = 0.7 V are shown in Figs. 5(a), 5(b) and Figs. 6(a), 6(b) respectively. The electrostatic surface potential is an important parameter to decide the threshold voltage of device. The surface potential parameter can be optimized by adjusting the metal work function of gate electrode and channel doping of SOI FinFET. The higher value of surface potential at low value of spacer is due to abrupt change in field distribution and improves the drain-induced barrier lowering (DIBL) and SCEs. On increasing the spacer length the potential at drain side decreases and drain conductance (g_d) of device drops down which in turn improves the intrinsic gain of the device or improves the analog performance of the device. The number of peaks near the drain side in the electron mobility profile decides the carrier transport efficiency which in turn affects the I_on of SOI FinFET. As the spacer length increases from 2 to 16 nm, the number of peaks increases and I_on of device degrades at high spacer value. Further I_on improves at high value of V_DS which can be analyzed in Fig. 6(b).

Figure 5. (Color online) Simulated results of SOI FinFET along the channel position (source to drain, left to right) at different spacer length for electrostatic potential at (a) V_DS = 0.05 V, (b) V_DS = 0.7 V.

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Figure 6. (Color online) Simulated results of SOI FinFET along the channel position (source to drain, left to right) at different spacer length for electron mobility at (a) V_DS = 0.05 V, (b) V_DS = 0.7 V.

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3.2 Device scalability and analog/RF performance

Drain current against gate voltage (I_D–V_GS) characteristics for SOI FinFET both in log and linear scales at V_DS = 0.05 V and V_DS = 0.7 V for different values of spacer lengths are shown in Figs. 7(a) and 7(b) respectively. The threshold voltage V_th for all spacer values are set to 0.2 V for V_DS = 0.7 V for fair comparison of performance characteristics. It is observed from theI_D–V_GS characteristics that on increasing the value of spacer length the drain current performance degraded due to degradation of electrostatic potential near the drain side.

Figure 7. (Color online) I_D–V_GS characteristics for SOI FinFET at different spacer length in log and linear scales for (a) V_DS = 0.05 V, (b) V_DS = 0.7 V.

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The main electrostatic figures of merit like sub-threshold slope (SS), trans-conductance generation factor (TGF = g_m/I_d), ON current (I_on), OFF current (I_off), analog figures of merit like output conductance (g_d), trans-conductance (g_m), intrinsic gain (A_V) and RF figures of merit like gate capacitance (C_gg) and cut off frequency (f_T) are evaluated at V_DS = 0.05 V and V_DS = 0.7 V to explore the performance for SOI FinFET device.

A plot of trans-conductance generation factor (TGF) and trans-conductance (g_m) versus V_GS voltage characteristics for different values of spacer lengths at V_DS = 0.05 V and V_DS = 0.7 V are shown in Figs. 8(a) and 8(b) respectively. The trans-conductance (g_m) parameter of the device is an important parameter, which affects the gain of the amplifier and is calculated according to Eq. (1). TGF signifies the effective uses of device current to get desired value of g_m. The high TGF means effective realization of analog circuits and operated with low value of supply voltage. TGF is calculated according to Eq. (2).

${g_{\rm m}} = \frac{{\partial {I_{\rm D}}}}{{\partial {V_{\rm GS}}}},$

(1)

${\rm {TGF}} = \frac{{{g_{\rm m}}}}{{{I_{\rm D}}}}.$

(2)

From the characteristics shown in Figs. 8(a) and 8(b), the value of g_m decreases on increasing the spacer length while the value of TGF improves due to more degradation in drain current compared to trans-conductance g_m for high value of spacer length.

Figure 8. (Color online) Trans-conductance (g_m) and trans-conductance generation factor (TGF) against V_GS characteristics for SOI FinFET at different spacer length for (a) V_DS = 0.05 V, (b) V_DS = 0.7 V.

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A combination of g_d (output conductance) and I_D (drain current) for different values of spacer length with function of V_DS (drain-to-source voltage) for the value of V_GS = 0.35 V and V_GS = 0.7 V for SOI FinFET are shown in Figs. 9(a) and 9(b) respectively. It is essential requirement of low value of output conductance (g_d) in order to have a large value of gain for analog circuit design. High value of g_d means low output resistance which increases the drain current with V_DS in saturation and this effect is known as channel length modulation. At low bias point of V_DS there is much variation of g_d but at high bias point of V_DS almost constant and same order of g_d is obtained for all values of spacer lengths.

Figure 9. (Color online) Output conductance (g_d) and drain current (I_D) against V_DS characteristics for SOI FinFET at different spacer length for (a) V_DS = 0.35 V, (b) V_DS = 0.7 V.

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The RF or high-frequency performance of SOI FinFET is evaluated by cut off frequency (f_T). A plot of C_gg (gate capacitance) and cut off frequency (f_T) against of V_GS (gate-to-source voltage) for different values of spacer lengths are evaluated at V_DS = 0.05 V and V_DS = 0.7 V and shown in Figs. 10(a), 10(b) and Figs. 11(a) and 11(b) respectively.

At low value of spacer region gate capacitance (C_gg) increases due to more fringing field accumulation while at high value of spacer length fringing field distributed along the spacer length hence gate capacitance (C_gg) decreases.

Figure 10. (Color online) C_gg (gate capacitance) against V_GS characteristics for SOI FinFET at different spacer length for (a) V_DS = 0.05 V, (b) V_DS = 0.7 V.

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At high value of spacer length on increasing the gate bias, degradation in cut off frequency (f_T) occurs due to degradation of trans-conductance value g_m as shown in Figs. 11(a) and 11(b) for SOI FinFET device.

Figure 11. (Color online) f_T (Cut-off frequency) against V_GS characteristics for SOI FinFET at different spacer length for (a) V_DS = 0.05 V, (b) V_DS = 0.7 V.

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All device scalability, analog and RF performance parameters for different values of spacer length from 2 to 16 nm are evaluated at V_DS = 0.05 V and V_DS = 0.7 V and shown in Tables 2 and 3 respectively. It is noticed from the simulated results in the Tables 2 and 3 that at V_DS = 0.05 V and V_DS = 0.7 V, on increasing the spacer lengths, there is an improvement in the digital performance parameters like SS, I_off, I_on/I_off and TGF with compromising in analog performance parameters like I_on and g_m. At V_DS = 0.05 V, the 12 nm value of spacer length gives high value of gain 59.73 dB and optimum cut-off frequency 123 GHz with compromising in I_on current compared to the 2 nm spacer length. This high gain is due to more reduction of output conductance g_d compared to reduction in trans-conductance g_m. Similarly, at V_DS = 0.7 V, 12 nm spacer length gives improved gain value with optimum cut-off frequency and slightly compromises in the digital performances. So, at low and high drain bias points, 12 nm gives better analog performance with optimum RF performance with compromising in digital performance.

Table 2. Simulated results at different spacer length for SOI FinFET at V_DS = 0.05 V.

Device spacer region, L_{sp, hk}	SS (mV/decade)	I_on (μA)	I_off (nA)	I_on/I_off	TGF (V⁻¹)	g_m (S)	g_d (S)	C_gg (fF)	f_T (GHz)	Gain, A_V (g_m/g_d) (dB)
2 nm	74.38	67.49	57.99	1163.8	30.8	1.05 × 10⁻⁴	4.99 × 10⁻⁷	0.202	83.1	46.46
5 nm	66.41	57.67	30.45	1893.9	35.7	9.28 × 10⁻⁵	1.23 × 10⁻⁷	0.131	113	57.55
8 nm	64.87	50.56	25.13	2011.9	36.8	8.91 × 10⁻⁵	1.43 × 10⁻⁷	0.113	126	55.89
12 nm	64.15	42.04	22.02	1909.2	37.5	8.31 × 10⁻⁵	8.57 × 10⁻⁸	0.108	123	59.73
16 nm	64.91	18.54	1.61	11515.5	39.4	5.37 × 10⁻⁵	5.71 × 10⁻⁸	0.112	76.3	59.47

DownLoad: CSV | Show Table

Table 3. Simulated results at different spacer length for SOI FinFET at V_DS = 0.7 V.

Device spacer region, L_{sp, hk}	SS (mV/decade)	I_on (μA)	I_off (nA)	I_on/I_off	TGF (V⁻¹)	g_m (S)	g_d (S)	C_gg (fF)	f_T (GHz)	Gain, A_V (g_m/g_d)(dB)
2 nm	83.53	106.80	185.85	574.7	25	2.15 × 10⁻⁴	1.14 × 10⁻⁵	0.210	163	25.5
5 nm	69.89	100.23	58.56	1711.6	32.5	2.02 × 10⁻⁴	5.54 × 10⁻⁶	0.150	215	31.24
8 nm	66.62	96.80	39.83	2430.3	34.9	1.96 × 10⁻⁴	4.14 × 10⁻⁶	0.133	235	33.50
12 nm	65.11	92.56	31.36	2951.5	36.1	1.89 × 10⁻⁴	2.25 × 10⁻⁶	0.137	219	38.48
16 nm	65.12	31.23	2.19	14260.3	39.3	4.35 × 10⁻⁵	7.30 × 10⁻⁷	0.681	102	35.50

DownLoad: CSV | Show Table

The main analog performance parameters like TGF, early voltage (V_EA) and intrinsic gain (g_m/g_d) are also evaluated at V_DS = V_DD/2 = 0.35 V for different values of spacer length for further exploring the analog performance of SOI FinFET. Early voltage (I_D/g_d) versus V_DS and intrinsic gain (g_m/g_d) versus V_GS characteristics for SOI FinFET for different spacer lengths are shown in Fig. 12. The evaluated parameters obtained by simulation process are shown in Table 4. It is noticed from Fig. 12 and the evaluated results given in Table 4 that at V_DS = V_DD/2, early voltage and TGF improves from 2 to 16 nm spacer length while intrinsic gain degrades after 12 nm spacer length due to more degradation in g_m value for SOI FinFET. Intrinsic gain is the key parameter for analog design and optimum value of intrinsic gain can be obtained with compromising in early voltage and TGF value of SOI FinFET device.

Figure 12. (Color online) I_D/g_d versus V_DS and g_m/g_d (intrinsic gain) versus V_GS characteristics for SOI FinFET for different spacer length at V_DS = 0.35 V.

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Table 4. Analog performance at different spacer length for SOI FinFET at V_DS = V_DD/2 = 0.35 V.

Device spacer region, L_{sp, hk}	g_m (S)	g_d (S)	g_m/g_d (dB)	V_EA (V)	TGF (V⁻¹)
2 nm	2.02 × 10⁻⁴	8.03 × 10⁻⁶	28.03	4.01	25
5 nm	1.99 × 10⁻⁴	4.72 × 10⁻⁶	32.50	6.45	32.5
8 nm	1.96 × 10⁻⁴	3.37 × 10⁻⁶	35.29	8.67	34.9
12 nm	1.85 × 10⁻⁴	2.86 × 10⁻⁶	36.21	9.70	36.1
16 nm	4.39 × 10⁻⁵	7.18 × 10⁻⁷	35.72	24.15	39.3

DownLoad: CSV | Show Table

4. Conclusion

The electrostatic, analog and RF performance of symmetrical high-k spacer SOI FinFET explored with variation of spacer length at V_DS = 0.05 V and V_DS = 0.7 V. Important figures of merit like electric field, electrostatic potential, electron mobility, sub-threshold slope (SS), trans-conductance generation factor (TGF = g_m/I_d), ON current (I_on), OFF current (I_off), output conductance (g_d), trans-conductance (g_m), intrinsic gain (A_V), gate capacitance (C_gg) and cut-off frequency (f_T) are closely demonstrated at different values of spacer length to explore the performance of SOI FinFET device. Analog performance is also evaluated at V_DS = V_DD/2 for 2 to 16 nm spacer lengths and concludes that the optimum analog/RF performance can be obtained around 12 nm spacer length.

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[13]	Vishvakarma S K, Agrawal V, Raj B, et al. Two dimensional analytical potential modeling of nanoscale symmetric double gate (SDG) MOSFET with ultra thin body (UTB). J Comput Theor Nanosci, 2007, 4(6): 1144 doi: 10.1166/jctn.2007.2390
[14]	Raj B, Saxena A K, Dasgupta S. Analytical modeling for the estimation of leakage current and subthreshold swing factor of nanoscale double gate FinFET device. Microelectron Int, 2009, 26(1): 53 doi: 10.1108/13565360910923188
[15]	Sharma V K, Pattanaik M, Raj B. INDEP approach for leakage reduction in nanoscale CMOS circuits. Int J Electron, 2015, 102(2): 200 doi: 10.1080/00207217.2014.896042
[16]	Raj B, Saxena A K, Dasgupta S. A compact drain current and threshold voltage quantum mechanical analytical modeling for FinFETs. J Nanoelectron Optoelectron, 2008,3(2):163 doi: 10.1166/jno.2008.209
[17]	Raj B. Quantum mechanical potential modeling of FinFET. In: Toward Quantum FinFET. Springer, 2013
[18]	Singh N, Lim F Y, Fang W W, et al. Ultra-narrow silicon nanowire gate-all-around CMOS devices: Impact of diameter, channel-orientation and low temperature on device performance. Technical Digest–International Electron Devices Meeting, 2006
[19]	Sharma V K, Pattanaik M, Raj B. PVT variations aware low leakage INDEP approach for nanoscale CMOS circuits. Microelectron Reliab, 2014, 54(1): 90 doi: 10.1016/j.microrel.2013.09.018
[20]	Nandi A, Saxena A K, Dasgupta S. Impact of dual-k spacer on analog performance of underlap FinFET. Microelectron J, 2012, 43(11): 883 doi: 10.1016/j.mejo.2012.06.001
[21]	Sachid A B, Manoj C R, Sharma D K, et al. Gate fringe-induced barrier lowering in underlap FinFET structures and its optimization. IEEE Electron Device Lett, 2008, 29(1): 128 doi: 10.1109/LED.2007.911974
[22]	Kranti A, Chung T M, Raskin J P. Analysis of static and dynamic performance of short-channel double-gate silicon-on-insulator metal–oxide–semiconductor field-effect transistors for improved cutoff frequency. Jpn J Appl Phy, 2005, 44(4S): 2340
[23]	Lim T C,Armstrong G A. The impact of the intrinsic and extrinsic resistances of double gate SOI on RF performance. Solid State Electron, 2006, 50(5): 774 doi: 10.1016/j.sse.2006.04.010
[24]	Liang X, Taur Y. A 2-D analytical solution for SCEs in DG MOSFETs. IEEE Trans Electron Devices, 2004, 51(9): 1385 doi: 10.1109/TED.2004.832707
[25]	Taur Y, Liang X, Wang W, et al. A continuous, analytic drain-current model for DG MOSFETs. IEEE Electron Device Lett, 2004, 25(2): 107 doi: 10.1109/LED.2003.822661
[26]	Vandooren A, Cristoloveanu S, Colinge J P. Hall mobility measurement in double-gate SOI MOSFETs SOI Conference. IEEE International (IEEE), 2000: 118
[27]	Khan H R, Mamaluy D, Vasileska D. Approaching optimal characteristics of 10-nm high-performance devices: A quantum transport simulation study of Si FinFET. IEEE Trans Electron Devices, 2008, 55(3): 743 doi: 10.1109/TED.2007.915387
[28]	Uchida K, Koga J, Takagi S. Experimental study on carrier transport mechanisms in double-and single-gate ultrathin-body MOSFETs-Coulomb scattering, volume inversion, and d T_SOI-induced scattering. IEEE International Electron Devices Meeting, 2003: 33
[29]	Dixit A, Kottantharayil A, Collaert N, et al. Analysis of the parasitic S/D resistance in multiple-gate FETs. IEEE Trans Electron Devices, 2005, 52(6): 1132 doi: 10.1109/TED.2005.848098
[30]	Kedzierski J, Ieong M, Nowak E, et al. Extension and source/drain design for high-performance FinFET devices. IEEE Trans Electron Devices, 2003, (4): 952
[31]	Tekleab D, Samavedam S , Zeitzoff P. Modeling and analysis of parasitic resistance in double-gate FinFETs. IEEE Trans Electron Devices, 2009, 56(10): 2291 doi: 10.1109/TED.2009.2028377
[32]	Matsukawa T, Endo K, Ishikawa Y, et al. Impact of extension and source/drain resistance on FinFET performance. IEEE International SOI Conference, 2008: 159
[33]	Rösner W, Landgraf E, Kretz J, et al. Nanoscale FinFETs for low power applications. Solid State Electron, 2004, 48(10): 1819
[34]	Kranti A , Armstrong G A. Source/drain extension region engineering in FinFETs for low-voltage analog applications. IEEE Electron Device Lett, 2007, 28(2): 139 doi: 10.1109/LED.2006.889239
[35]	Yu B, Y Bin, Chang L C L, et al. FinFET scaling to 10 nm gate length. Dig Int Electron Devices Meet, 2002: 251
[36]	Patil G C, Qureshi S. Engineering spacers in dopant-segregated Schottky barrier SOI MOSFET for nanoscale CMOS logic circuits. Semicond Sci Technol, 2012, 27(4): 045004 doi: 10.1088/0268-1242/27/4/045004
[37]	Pal P K, Kaushik B K, Dasgupta S. Asymmetric Dual-Spacer Trigate FinFET Device-Circuit Codesign and Its Variability Analysis. IEEE Trans. Electron Devices, 2015, 62(4): 1105 doi: 10.1109/TED.2015.2400053
[38]	Goel A, Gupta S K, Roy K. Asymmetric drain spacer extension (ADSE) FinFETs for low-power and robust SRAMs. IEEE Trans Electron Devices, 2011, 58(2): 296 doi: 10.1109/TED.2010.2090421
[39]	Magnone P, Mercha A, Subramanian V, et al. Matching performance of FinFET devices with fin widths down to 10 nm. IEEE Electron Device Lett, 2009, 30(12): 1374 doi: 10.1109/LED.2009.2034117
[40]	Nowak EJ. Maintaining the benefits of CMOS scaling when scaling bogs down. IBM J Res Dev, 2002, 46(2.3): 169 doi: 10.1147/rd.462.0169
[41]	http://www.synopsys.com/. Sentaurus TCAD User’s Manual. In: Synopsys Sentaurus Device. 2009
[42]	Pradhan K P, Mohapatra S K, Sahu P K, et al. Impact of high-k gate dielectric on analog and RF performance of nanoscale DG-MOSFET. Microelectronics J, 2014, 45(2): 144 doi: 10.1016/j.mejo.2013.11.016
[43]	Ho B, Sun X, Shin C, et al. Design optimization of multigate bulk MOSFETs. IEEE Trans Electron Devices, 2013, 60(1): 28 doi: 10.1109/TED.2012.2224870
[44]	De Andrade M G C, Martino J A, Aoulaiche M, et al. Behavior of triple-gate Bulk FinFETs with and without DTMOS operation. Solid-State Electron, 2012, 71: 63 doi: 10.1016/j.sse.2011.10.022
[45]	ITRS. International technology roadmap for semiconductors, 2013
[46]	Canali C, Majni G, Minder R, et al. Electron and hole drift velocity measurements in silicon and their empirical relation to electric field and temperature. IEEE Trans Electron Devices, 1975, 22(11): 1045 doi: 10.1109/T-ED.1975.18267
[47]	Lombardi C, Manzini S, Saporito A, et al. A physically based mobility model for numerical simulation of nonplanar devices. IEEE Trans Comput Des Integr Circuits Syst, 1988, 7(11): 1164 doi: 10.1109/43.9186
[48]	Shockley W, Read W T. Statistics of the recombination of holes and electrons. Phys Rev, 1952, 87(46): 835
[49]	Hall R N. Electron-hole recombination in germanium. Phys Rev, 1952, 87(2): 387

Fig. 1. (Color online) (a) Symmetrical high-k spacer SOI FinFET (Device-D1). (b) Cross-section view of Device-D1.

DownLoad: Full-Size Img PowerPoint

Fig. 2. (Color online) Simulated results of SOI FinFET along the channel position (source to drain, left to right) at different spacer length for electric field, E_x component at (a) V_DS = 0.05 V, (b) V_DS = 0.7 V.

DownLoad: Full-Size Img PowerPoint

Fig. 3. (Color online) Simulated results of SOI FinFET along the channel position (source to drain, left to right) at different spacer length for electric field, E_Z component at (a) V_DS = 0.05 V, (b) V_DS = 0.7 V.

DownLoad: Full-Size Img PowerPoint

Fig. 4. (Color online) Simulated results of SOI FinFET along the channel position (source to drain, left to right) at different spacer length for total effective electric field, component at (a) V_DS = 0.05 V, (b) V_DS = 0.7 V.

DownLoad: Full-Size Img PowerPoint

Fig. 5. (Color online) Simulated results of SOI FinFET along the channel position (source to drain, left to right) at different spacer length for electrostatic potential at (a) V_DS = 0.05 V, (b) V_DS = 0.7 V.

DownLoad: Full-Size Img PowerPoint

Fig. 6. (Color online) Simulated results of SOI FinFET along the channel position (source to drain, left to right) at different spacer length for electron mobility at (a) V_DS = 0.05 V, (b) V_DS = 0.7 V.

DownLoad: Full-Size Img PowerPoint

Fig. 7. (Color online) I_D–V_GS characteristics for SOI FinFET at different spacer length in log and linear scales for (a) V_DS = 0.05 V, (b) V_DS = 0.7 V.

DownLoad: Full-Size Img PowerPoint

Fig. 8. (Color online) Trans-conductance (g_m) and trans-conductance generation factor (TGF) against V_GS characteristics for SOI FinFET at different spacer length for (a) V_DS = 0.05 V, (b) V_DS = 0.7 V.

DownLoad: Full-Size Img PowerPoint

Fig. 9. (Color online) Output conductance (g_d) and drain current (I_D) against V_DS characteristics for SOI FinFET at different spacer length for (a) V_DS = 0.35 V, (b) V_DS = 0.7 V.

DownLoad: Full-Size Img PowerPoint

Fig. 10. (Color online) C_gg (gate capacitance) against V_GS characteristics for SOI FinFET at different spacer length for (a) V_DS = 0.05 V, (b) V_DS = 0.7 V.

DownLoad: Full-Size Img PowerPoint

Fig. 11. (Color online) f_T (Cut-off frequency) against V_GS characteristics for SOI FinFET at different spacer length for (a) V_DS = 0.05 V, (b) V_DS = 0.7 V.

DownLoad: Full-Size Img PowerPoint

Fig. 12. (Color online) I_D/g_d versus V_DS and g_m/g_d (intrinsic gain) versus V_GS characteristics for SOI FinFET for different spacer length at V_DS = 0.35 V.

DownLoad: Full-Size Img PowerPoint

Table 1. Dimensional values used for simulation in this paper.

Parameter	Description	Device-D1
W_Fin	Fin width	10 nm
H_Fin	Fin height	26 nm
L_g	Gate channel length	20 nm
t_ox	Oxide thickness	0.9 nm
BOX	Thickness of buried oxide	40 nm
L_{sp, hk}	High-k (HfO₂, k = 22) spacer length under source/drain side	2–16 nm
W_s/d	Source/drain width	40 nm

DownLoad: CSV

Table 2. Simulated results at different spacer length for SOI FinFET at V_DS = 0.05 V.

Device spacer region, L_{sp, hk}	SS (mV/decade)	I_on (μA)	I_off (nA)	I_on/I_off	TGF (V⁻¹)	g_m (S)	g_d (S)	C_gg (fF)	f_T (GHz)	Gain, A_V (g_m/g_d) (dB)
2 nm	74.38	67.49	57.99	1163.8	30.8	1.05 × 10⁻⁴	4.99 × 10⁻⁷	0.202	83.1	46.46
5 nm	66.41	57.67	30.45	1893.9	35.7	9.28 × 10⁻⁵	1.23 × 10⁻⁷	0.131	113	57.55
8 nm	64.87	50.56	25.13	2011.9	36.8	8.91 × 10⁻⁵	1.43 × 10⁻⁷	0.113	126	55.89
12 nm	64.15	42.04	22.02	1909.2	37.5	8.31 × 10⁻⁵	8.57 × 10⁻⁸	0.108	123	59.73
16 nm	64.91	18.54	1.61	11515.5	39.4	5.37 × 10⁻⁵	5.71 × 10⁻⁸	0.112	76.3	59.47

DownLoad: CSV

Table 3. Simulated results at different spacer length for SOI FinFET at V_DS = 0.7 V.

Device spacer region, L_{sp, hk}	SS (mV/decade)	I_on (μA)	I_off (nA)	I_on/I_off	TGF (V⁻¹)	g_m (S)	g_d (S)	C_gg (fF)	f_T (GHz)	Gain, A_V (g_m/g_d)(dB)
2 nm	83.53	106.80	185.85	574.7	25	2.15 × 10⁻⁴	1.14 × 10⁻⁵	0.210	163	25.5
5 nm	69.89	100.23	58.56	1711.6	32.5	2.02 × 10⁻⁴	5.54 × 10⁻⁶	0.150	215	31.24
8 nm	66.62	96.80	39.83	2430.3	34.9	1.96 × 10⁻⁴	4.14 × 10⁻⁶	0.133	235	33.50
12 nm	65.11	92.56	31.36	2951.5	36.1	1.89 × 10⁻⁴	2.25 × 10⁻⁶	0.137	219	38.48
16 nm	65.12	31.23	2.19	14260.3	39.3	4.35 × 10⁻⁵	7.30 × 10⁻⁷	0.681	102	35.50

DownLoad: CSV

Table 4. Analog performance at different spacer length for SOI FinFET at V_DS = V_DD/2 = 0.35 V.

Device spacer region, L_{sp, hk}	g_m (S)	g_d (S)	g_m/g_d (dB)	V_EA (V)	TGF (V⁻¹)
2 nm	2.02 × 10⁻⁴	8.03 × 10⁻⁶	28.03	4.01	25
5 nm	1.99 × 10⁻⁴	4.72 × 10⁻⁶	32.50	6.45	32.5
8 nm	1.96 × 10⁻⁴	3.37 × 10⁻⁶	35.29	8.67	34.9
12 nm	1.85 × 10⁻⁴	2.86 × 10⁻⁶	36.21	9.70	36.1
16 nm	4.39 × 10⁻⁵	7.18 × 10⁻⁷	35.72	24.15	39.3

DownLoad: CSV

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[11]	Park J T, Colinge J P, Diaz C H. Pi-gate SOI MOSFET. IEEE Electron Device Lett, 2001, 22(8): 405 doi: 10.1109/55.936358
[12]	Colinge J P, Chandrakasan A. FinFETs and other multi-gate transistors. Springer, 2008
[13]	Vishvakarma S K, Agrawal V, Raj B, et al. Two dimensional analytical potential modeling of nanoscale symmetric double gate (SDG) MOSFET with ultra thin body (UTB). J Comput Theor Nanosci, 2007, 4(6): 1144 doi: 10.1166/jctn.2007.2390
[14]	Raj B, Saxena A K, Dasgupta S. Analytical modeling for the estimation of leakage current and subthreshold swing factor of nanoscale double gate FinFET device. Microelectron Int, 2009, 26(1): 53 doi: 10.1108/13565360910923188
[15]	Sharma V K, Pattanaik M, Raj B. INDEP approach for leakage reduction in nanoscale CMOS circuits. Int J Electron, 2015, 102(2): 200 doi: 10.1080/00207217.2014.896042
[16]	Raj B, Saxena A K, Dasgupta S. A compact drain current and threshold voltage quantum mechanical analytical modeling for FinFETs. J Nanoelectron Optoelectron, 2008,3(2):163 doi: 10.1166/jno.2008.209
[17]	Raj B. Quantum mechanical potential modeling of FinFET. In: Toward Quantum FinFET. Springer, 2013
[18]	Singh N, Lim F Y, Fang W W, et al. Ultra-narrow silicon nanowire gate-all-around CMOS devices: Impact of diameter, channel-orientation and low temperature on device performance. Technical Digest–International Electron Devices Meeting, 2006
[19]	Sharma V K, Pattanaik M, Raj B. PVT variations aware low leakage INDEP approach for nanoscale CMOS circuits. Microelectron Reliab, 2014, 54(1): 90 doi: 10.1016/j.microrel.2013.09.018
[20]	Nandi A, Saxena A K, Dasgupta S. Impact of dual-k spacer on analog performance of underlap FinFET. Microelectron J, 2012, 43(11): 883 doi: 10.1016/j.mejo.2012.06.001
[21]	Sachid A B, Manoj C R, Sharma D K, et al. Gate fringe-induced barrier lowering in underlap FinFET structures and its optimization. IEEE Electron Device Lett, 2008, 29(1): 128 doi: 10.1109/LED.2007.911974
[22]	Kranti A, Chung T M, Raskin J P. Analysis of static and dynamic performance of short-channel double-gate silicon-on-insulator metal–oxide–semiconductor field-effect transistors for improved cutoff frequency. Jpn J Appl Phy, 2005, 44(4S): 2340
[23]	Lim T C,Armstrong G A. The impact of the intrinsic and extrinsic resistances of double gate SOI on RF performance. Solid State Electron, 2006, 50(5): 774 doi: 10.1016/j.sse.2006.04.010
[24]	Liang X, Taur Y. A 2-D analytical solution for SCEs in DG MOSFETs. IEEE Trans Electron Devices, 2004, 51(9): 1385 doi: 10.1109/TED.2004.832707
[25]	Taur Y, Liang X, Wang W, et al. A continuous, analytic drain-current model for DG MOSFETs. IEEE Electron Device Lett, 2004, 25(2): 107 doi: 10.1109/LED.2003.822661
[26]	Vandooren A, Cristoloveanu S, Colinge J P. Hall mobility measurement in double-gate SOI MOSFETs SOI Conference. IEEE International (IEEE), 2000: 118
[27]	Khan H R, Mamaluy D, Vasileska D. Approaching optimal characteristics of 10-nm high-performance devices: A quantum transport simulation study of Si FinFET. IEEE Trans Electron Devices, 2008, 55(3): 743 doi: 10.1109/TED.2007.915387
[28]	Uchida K, Koga J, Takagi S. Experimental study on carrier transport mechanisms in double-and single-gate ultrathin-body MOSFETs-Coulomb scattering, volume inversion, and d T_SOI-induced scattering. IEEE International Electron Devices Meeting, 2003: 33
[29]	Dixit A, Kottantharayil A, Collaert N, et al. Analysis of the parasitic S/D resistance in multiple-gate FETs. IEEE Trans Electron Devices, 2005, 52(6): 1132 doi: 10.1109/TED.2005.848098
[30]	Kedzierski J, Ieong M, Nowak E, et al. Extension and source/drain design for high-performance FinFET devices. IEEE Trans Electron Devices, 2003, (4): 952
[31]	Tekleab D, Samavedam S , Zeitzoff P. Modeling and analysis of parasitic resistance in double-gate FinFETs. IEEE Trans Electron Devices, 2009, 56(10): 2291 doi: 10.1109/TED.2009.2028377
[32]	Matsukawa T, Endo K, Ishikawa Y, et al. Impact of extension and source/drain resistance on FinFET performance. IEEE International SOI Conference, 2008: 159
[33]	Rösner W, Landgraf E, Kretz J, et al. Nanoscale FinFETs for low power applications. Solid State Electron, 2004, 48(10): 1819
[34]	Kranti A , Armstrong G A. Source/drain extension region engineering in FinFETs for low-voltage analog applications. IEEE Electron Device Lett, 2007, 28(2): 139 doi: 10.1109/LED.2006.889239
[35]	Yu B, Y Bin, Chang L C L, et al. FinFET scaling to 10 nm gate length. Dig Int Electron Devices Meet, 2002: 251
[36]	Patil G C, Qureshi S. Engineering spacers in dopant-segregated Schottky barrier SOI MOSFET for nanoscale CMOS logic circuits. Semicond Sci Technol, 2012, 27(4): 045004 doi: 10.1088/0268-1242/27/4/045004
[37]	Pal P K, Kaushik B K, Dasgupta S. Asymmetric Dual-Spacer Trigate FinFET Device-Circuit Codesign and Its Variability Analysis. IEEE Trans. Electron Devices, 2015, 62(4): 1105 doi: 10.1109/TED.2015.2400053
[38]	Goel A, Gupta S K, Roy K. Asymmetric drain spacer extension (ADSE) FinFETs for low-power and robust SRAMs. IEEE Trans Electron Devices, 2011, 58(2): 296 doi: 10.1109/TED.2010.2090421
[39]	Magnone P, Mercha A, Subramanian V, et al. Matching performance of FinFET devices with fin widths down to 10 nm. IEEE Electron Device Lett, 2009, 30(12): 1374 doi: 10.1109/LED.2009.2034117
[40]	Nowak EJ. Maintaining the benefits of CMOS scaling when scaling bogs down. IBM J Res Dev, 2002, 46(2.3): 169 doi: 10.1147/rd.462.0169
[41]	http://www.synopsys.com/. Sentaurus TCAD User’s Manual. In: Synopsys Sentaurus Device. 2009
[42]	Pradhan K P, Mohapatra S K, Sahu P K, et al. Impact of high-k gate dielectric on analog and RF performance of nanoscale DG-MOSFET. Microelectronics J, 2014, 45(2): 144 doi: 10.1016/j.mejo.2013.11.016
[43]	Ho B, Sun X, Shin C, et al. Design optimization of multigate bulk MOSFETs. IEEE Trans Electron Devices, 2013, 60(1): 28 doi: 10.1109/TED.2012.2224870
[44]	De Andrade M G C, Martino J A, Aoulaiche M, et al. Behavior of triple-gate Bulk FinFETs with and without DTMOS operation. Solid-State Electron, 2012, 71: 63 doi: 10.1016/j.sse.2011.10.022
[45]	ITRS. International technology roadmap for semiconductors, 2013
[46]	Canali C, Majni G, Minder R, et al. Electron and hole drift velocity measurements in silicon and their empirical relation to electric field and temperature. IEEE Trans Electron Devices, 1975, 22(11): 1045 doi: 10.1109/T-ED.1975.18267
[47]	Lombardi C, Manzini S, Saporito A, et al. A physically based mobility model for numerical simulation of nonplanar devices. IEEE Trans Comput Des Integr Circuits Syst, 1988, 7(11): 1164 doi: 10.1109/43.9186
[48]	Shockley W, Read W T. Statistics of the recombination of holes and electrons. Phys Rev, 1952, 87(46): 835
[49]	Hall R N. Electron-hole recombination in germanium. Phys Rev, 1952, 87(2): 387

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13	Physical properties of spray deposited CdTe thin films: PEC performance V. M. Nikale, S. S. Shinde, C. H. Bhosale, K.Y. Rajpure Journal of Semiconductors, 2011, 32(3): 033001. doi: 10.1088/1674-4926/32/3/033001
14	A two-dimensional analytical-model-based comparative threshold performance analysis of SOI-SON MOSFETs Sanjoy Deb, Saptarsi Ghosh, N Basanta Singh, A K De, Subir Kumar Sarkar, et al. Journal of Semiconductors, 2011, 32(10): 104001. doi: 10.1088/1674-4926/32/10/104001
15	A high-performance, low-power ΣΔ ADC for digital audio applications Luo Hao, Han Yan, Ray C. C. Cheung, Han Xiaoxia, Ma Shaoyu, et al. Journal of Semiconductors, 2010, 31(5): 055009. doi: 10.1088/1674-4926/31/5/055009
16	Noise performance in AlGaN/GaN HEMTs under high drain bias Pang Lei, Pu Yan, Liu Xinyu, Wang Liang, Liu Jian, et al. Journal of Semiconductors, 2009, 30(8): 084004. doi: 10.1088/1674-4926/30/8/084004
17	A novel GAAC FinFET transistor: device analysis, 3D TCAD simulation, and fabrication Xiao Deyuan, Wang Xi, Yuan Haijiang, Yu Yuehui, Xie Zhifeng, et al. Journal of Semiconductors, 2009, 30(1): 014001. doi: 10.1088/1674-4926/30/1/014001
18	Full-Chip Scalable Routing Framework Considering Congestion and Performance Yao Hailong, Cai Yici, Hong Xianlong, Zhou Qiang Chinese Journal of Semiconductors , 2006, 27(7): 1201-1208.
19	Design and Analysis of Analog Front-End of Passive RFID Transponders Hu Jianyun, He Yan, Min Hao Chinese Journal of Semiconductors , 2006, 27(6): 999-1005.
20	3-D Simulation of FINFET LIU En-feng, LIU Xiao-yan, HAN Ru-qi Chinese Journal of Semiconductors , 2002, 23(9): 909-913.

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Neeraj Jain, Balwinder Raj. Impact of underlap spacer region variation on electrostatic and analog performance of symmetrical high-k SOI FinFET at 20 nm channel length[J]. Journal of Semiconductors, 2017, 38(12): 122002. doi: 10.1088/1674-4926/38/12/122002

N Jain, B Raj. Impact of underlap spacer region variation on electrostatic and analog performance of symmetrical high-k SOI FinFET at 20 nm channel length[J]. J. Semicond., 2017, 38(12): 122002. doi: 10.1088/1674-4926/38/12/122002.

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Received: 29 January 2017 Revised: 26 May 2017 Online: Corrected proof: 15 November 2017Accepted Manuscript: 06 December 2017Published: 01 December 2017

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Neeraj Jain, Balwinder Raj. Impact of underlap spacer region variation on electrostatic and analog performance of symmetrical high-k SOI FinFET at 20 nm channel length[J]. Journal of Semiconductors, 2017, 38(12): 122002. doi: 10.1088/1674-4926/38/12/122002 ****N Jain, B Raj. Impact of underlap spacer region variation on electrostatic and analog performance of symmetrical high-k SOI FinFET at 20 nm channel length[J]. J. Semicond., 2017, 38(12): 122002. doi: 10.1088/1674-4926/38/12/122002.

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