Processing math: 100%
J. Semicond. > 2018, Volume 39 > Issue 11 > 115001
|

SEMICONDUCTOR INTEGRATED CIRCUITS

Berger code based concurrent online self-testing of embedded processors

G. Prasad Acharya1, and M. Asha Rani2

+ Author Affiliations

 Corresponding author: G. Prasad Acharya, gprasad04@gmail.com

DOI: 10.1088/1674-4926/39/11/115001

PDF

Turn off MathJax

Abstract: We propose an approach to detect the temporary faults induced by an environmental phenomenon called single event upset (SEU). Berger code based self-checking checkers provides an online detection of faults in digital circuits as well as in memory arrays. In this work, a concurrent Berger code based online self- testable architecture is proposed and integrated in 32-bit DLX reduced instruction set computer (RISC) processor on a single silicon chip. The proposed concurrent test methodology is implemented and verified for various arithmetic and logical operations of the DLX processor. The FPGA implementation of the proposed design shows that a meager increase in hardware utilization facilitates online self-testing to detect temporary faults.

Key words: single event upset, Berger code, DLX RISC, online testing

The transistor miniaturization and integration density in today’s VLSI technology is increasing at the rate predicted by Moore’s law and even at higher rates. Today’s multi-processor system on-chip (MPSoC), network on-chip (NoC) and graphics processing unit (GPU) technologies with high level integration of processing elements/cores are offering either server-based or cloud-based massively parallel processing. These processors play an important role in accelerating the computational speed in massively high data involved applications such as artificial intelligence in automobiles, drones and video surveillances. The SoC technology allows the integration of one or more processing cores (processors), embedded memory IPs and input/output (I/O) peripherals. RISC based processors are the backbones of application specific embedded systems. RISC provides a platform wherein a small-set of instructions are made available for specific tasks so that the execution takes place at much higher speed i.e. even more than millions of instructions per second.

The SoC architectures also include analog and mixed signal interfaces (analog-to-digital and digital-to-analog converters) that provide the interface between analog data acquisition units and digital processors. According to a survey[1], around 80% circuitry in SoCs is digital but 80% of faults occur in analog circuitry. Though the BIST techniques are basically developed for the detection of faults based on voltage-level based testing in digital circuits, these techniques are further developed to incorporate parametric testing for self-testing of analog circuits as well.

Due to sub-micron miniaturization and high integration density of transistors, today’s ICs are becoming more and more susceptible not only to manufacturing defects but also to the environmental disturbances such as single event upset (SEU). The SEU is a natural phenomenon wherein high energy particles like alpha and beta particles may fall onto the ICs and cause malfunctioning of the system due to the induction of temporary faults[2–6]. These faults are harder to detect during testing because these faults may not occur during test. On-line self-test methodologies available in many literatures are capable of detecting such types of temporary faults without system downtime.

This paper is organized as follows: Section 2 outlines the architecture and instruction format of the DLX RISC processor. The embedded processor testing methodologies are presented in Section 3. The proposed concurrent online self-test methodology is presented in Section 4. Section 5 discusses the experimental work presented in this paper. Finally, the concluding remarks are presented in Section 6.

The DLX is a 32-bit reduced instruction set computer (RISC) developed based on load-store and microprocessors without interleaving pipelining system (MIPS) architecture[7]. The DLX RISC processor is the simplest architecture (as shown in Fig. 1) used for academic purposes and is the basic architecture for commercially available RISC processors. The DLX architecture includes a register set of 32 registers each of size 32-bits wide and a 32-bit program counter (PC). The processor is based on a five-stage pipelining architecture. These pipeline stages are instruction fetch (IF), instruction decode (ID), execute (EX), memory access (MEM) and write back (WB).

Figure  1.  Architecture of DLX RISC processor.
DownLoad: Full-Size Img PowerPoint

During the IF stage, a 32-bit instruction will get fetched from the memory. The PC holds the address of the next instruction to be fetched (i) by incrementing PC by 4 in case of sequential execution and (ii) the branch target address predicted by the branch prediction logic. During the ID stage, the instruction decoder decodes the 32-bit instructions into various fields as given in Table 1 and determines the required operands and branching address. During the EXE stage, the arithmetic logic unit (ALU) performs the arithmetic and logical operations on the operands decoded/provided by the instruction decoder. During the MEM stage, the computed results will be written back to the data memory. The result will be written back into register during the WB stage. The MEM and WB cycles can be performed in a single clock cycle and hence the execution of an instruction can be completed in 4 clock cycles.

The ALU performs 32-bit integer and floating point (single and double precision) arithmetic operations and logical operations. All the instructions in DLX processors are 32-bit long and can be divided into the following three classes according to the type of operation: R (register)-type, I (immediate)-type and J (jump)-type. In R-type instructions, three registers (two source registers and one destination) are specified in the instructions. In I-type instructions, one source register and 16-bit immediate operand (sign extended to 32-bit) are used. The J-type instructions consist of 6-bit opcode and 26-bit operand. The destination address is calculated using the 26-bit operand value. Table 1 summarizes the instruction format of the DLX processor.

Figure  2.  Five stage pipelining of DLX processor.
DownLoad: Full-Size Img PowerPoint
Table  1.  Instruction formats of DLX RISC
Instruction type bits
31–26 25–21 20–16 15–11 10–0
R-type Opcode R1 R2 Rd Unused
I-type Opcode R1 R2 Immediate
J-type Opcode Operand value
DownLoad: CSV  | Show Table

The digital circuit testing techniques can be broadly classified into external testing and self-testing. The conventional method of testing the manufacturing defects in digital circuits is carried out using automatic test equipment (ATE) hardware. The quality test patterns are generated using algorithm based test pattern generation strategies as available in the related literatures and stored along with their expected responses in the ATE memory.

The hardware based self-testing (also known as built in self-test) of a processor facilitates the generation of test patterns using LFSR, application of the test patterns to the processor under test and the analysis of test responses for their functional correctness without the use of any external circuitry. The processor uses its internal resources such as the processor itself, the register file, instruction set, memory and other test support hardware. The major parameters to be considered while selecting the BIST strategy include: hardware overhead, test data generation and application time, performance degradation especially in critical paths in case of high performance devices and power consumption during self-testing. BIST capability is incorporated in a MIPS processor using a linear feedback shift register (LFSR), built-in logic block observer (BILBO) and concurrent BILBO (CBILBO)[8]. Various power saving techniques like weighted LFSR and dual speed LFSR have been presented to reduce the power consumption in the self-testable MIPS processor. The dynamic partial reconfiguration feature of FPGAs shall be utilized for self-testing of processor cores by dynamically reconfiguring the partial bit-files of the functional-mode processor and BIST-oriented processor onto the dynamic region of the FPGA[9].

The software-based self-testing (SBST)[10–15] provides an alternative solution for the above mentioned limitations of hardware based self-testing methodology. In this methodology, generation and application of test patterns for the processor under test and response analysis are carried out by specially written software routines executed on the processor itself. The self-test routine (software program) and test patterns are stored in the instruction memory and data memory of the processor respectively. A simplified processor model for software based self-testing is shown in Fig. 3.

Figure  3.  (Color online) Processor model for software-based self-testing.
DownLoad: Full-Size Img PowerPoint

The SBST is based on Instruction Set Architecture (ISA) and the Register Transfer Language (RTL) description of the processor, and the test engineer need not have the complete details of gate-level netlist and structural fault model. The processor executes the test programs at its actual speed and hence the SBST is capable of providing at-speed test solutions unlike to hardware-based BIST. However, the SBST is capable of providing at-speed self-test solutions to the processor for functionality verification both at the manufacturing and/or field level; it cannot substitute the structure based test approaches like BIST and hence can be used to supplement the structural based test approaches to provide a more quality test.

Most of the BIST approaches (either hardware or software based) found in the literature are off-line or non-concurrent test approaches. In these approaches either the functionality of the processor is to be suspended or the processor is to be switched into idle mode during test i.e., the test is not carried out concurrently with its functional operation. In the concurrent on-line self-test approach, which is the main contribution of this paper, both the functional and test operations will be carried out simultaneously. Refs. [16, 17] have presented the implementation of the self-checking register file and ALU using Berger code, no literature to the best knowledge of the authors is found in the direction of designing a self-checking processor. Since the Berger code forms the least redundant on-line unidirectional error detecting code, this paper has proposed a methodology to design a self-testable processor by incorporating a self-checking capability using the Berger code for the DLX RISC processor.

The major contribution for malfunctioning of digital circuits/systems in the field (while on operation) is due to the temporary (dynamic) faults. These faults may be caused by radiation and other hard environmental conditions. The SEU is the radiation-induced errors in microelectronic circuits that may change the behavior of dynamic circuits as well as memory devices. Since these faults are non-recurrent and harder to detect during a test using off-line BIST, on-line self-test methodologies are capable of detecting the temporary faults and are used to improve the reliability of the system. This paper presents the design of the Berger code based totally self-checking checkers (TSC) to detect both permanent stuck-at faults as well as temporary faults in the DLX RISC processor. Fig. 4 shows the generalized architecture for the proposed self-testable processor.

Figure  4.  Simplified architecture of proposed self-testable DLX processor.
DownLoad: Full-Size Img PowerPoint

4.1 Totally self-checking checkers using berger code

Among all unidirectional error detecting (AUED) codes, the Berger code forms the least redundant and separable code[18, 19]. The Berger code is available with two encoding schemes: B0 and B1. In the B0 encoding scheme of the Berger code used in this work, the check bits represent the binary equivalent of the number of zeros in the information bit sequence, I. In the B1 scheme of encoding, the check bits represent the 1’s complement of the number of 1’s in I. The number of check bits (k) for the information sequence of length n bits is evaluated using the inequality k=⌈log2(n+1)⌉ . The combinational circuit, C1 in Fig. 4 is a combinational circuit that produces the complement of the check bits, which is then fed to the 2-rail checker along with the k-check bits. The two rail-checker produces two complementary outputs f and g in the no fault case otherwise it produces identical values for f and g.

Combinational circuit, C1

A Berger code is said to be a maximal length Berger code has if n = (2k − 1) otherwise it is a non-maximal length Berger code. The combinational circuit C1 as shown in Fig. 4 produces an output which is the binary equivalent of the number of 1’s in the information sequence, I. In order to compute the check bits for the non-maximal length Berger code, we define a number m = I0 mod (k + 1), where I0 is the number of 0’s in the sequence I. The Berger code check bits are the binary equivalent of m and its length is equal to [log2(k + 1)].

Two-rail checker

The two-rail checker as shown in Fig. 5(a), is a 1-out-of-2 code which receives two groups of inputs X = (x1, x2, …xn) and Y = (y1, y2, …yn) from the functional circuit and produces two outputs f and g that are complementary to each other. As long as yi = (xi)| is satisfied, the outputs of the two-rail checker will be f = 0 and g = 1. The totally self-checking two-rail checker can be extended for any arbitrary pairs (xiyi and xi + 1yi + 1) of inputs as given in the structure of Fig. 5(b).

Figure  5.  (a) Self-checking 2-rail checker. (b) Self-checking 2-rail checker with 6 inputs.
DownLoad: Full-Size Img PowerPoint

4.2 Berger code predictions for ALU operations

The ALU is the heart of any processor and performs various arithmetic and logical operations. This section presents the predictions of the Berger code for various ALU operations. Consider two n-bit operands A = (an, an–1, …. a2, a1) and B = (bn, bn–1, …. b2, b1). Let Ac and Bc be the Berger code of A and B respectively.

Addition (Y = A + B + cin)

The Berger code of the sum (Yc) is computed as Yc = Ac + Bc − cin − Cc + cout, where cin, cout and Cc are input carry, output carry and the Berger code of intermediate carries C = (cn, cn–1, …. c2, c1) respectively.

Subtraction

The Berger code of the difference (Yc) is computed as Yc = Ac – Bc + bin + BIc – bout, where bin, bout and BIc are in borrow, output borrow and the Berger code of intermediate borrows BI = (bin, bin–1, …. bi2, bi1) respectively.

2’s complement subtraction (Y = A − B = A + B| + 1)

The Berger code of the sum (Yc) is computed as Yc = Ac-Bc − (cin)| − N(C) + cout, where cin, cout and N(C) are input carry, output carry and the number of 1’s in the intermediate carries C = (cn, cn–1, …. c2, c1) respectively.

Array Multiplier (Y = AB)

The Berger code of the multiplier output (Yc) is computed as Yc = 4Ac − 4Bc − AcBc − N(C) + 12, where N(c)=∑mi=1∑n−1j=1Ci,j and Ci, j are the carry generated by the full adder in the stage of the ith row and the jth column of the m-bit by n-bit array multiplier as shown in Fig. 6 (m = 4 and n = 4).

Figure  6.  4 × 4 binary array multiplier.
DownLoad: Full-Size Img PowerPoint

Logical-AND (Y = A.B)

The Berger code of the logical-AND output (Yc) is computed as Yc = Ac + Bc − Zc where Zc represents the Berger code of (A|B).

Logical-OR (Y = A|B)

The Berger code of the logical-OR output (Yc) is computed as Yc = Ac + Bc − Zc where Zc represents the Berger code of (A.B).

Logical-Inverter (Y = A|)

The Berger code of the logical-Inverter output (Yc) is computed as Yc = n − Ac.

Logical-XOR (Y = A^B)

The Berger code of the logical-XOR output (Yc) is computed as Yc = Ac + Bc − 2Zc + n where Zc represents the Berger code of (A.B).

The Berger code based totally self-checking checker (TSC) logic is incorporated for various arithmetic and logical operations within the RTL description of the DLX RISC processor and simulated using Xilinx Vivado 2017.2. Fig. 7 demonstrates the simulation waveform of the DLX processor. The 32-bit instruction Data_in = 0x04031040 is decoded as opcode = 01 (ADD operation), [RA] = 0x01, [RB] = 0x02. The result of the ADD operation is [RD] = 0x03. Similarly, Data_in = 0x0C062900 is decoded as opcode = 03 (Logical-OR operation), [RA] = 0x04, [RB] = 0x05. The result of the logical-OR operation is [RD] = 0x05.

To demonstrate the self-checking capability of the implemented processor, faults are injected in the design during simulation. The Stuck-at 1 (SA1) fault is injected in the cin line by forcing cin = 1, which produced the output result as [RD] = 0x04 as demonstrated in Fig. 8, instead of [RD] = 0x03 for the same instruction Data_in = 0x04031040 shown in Fig. 7. Similarly, bit-flip of the 27th bit and the 28th bit of Data_in = 0x0C062900 will be decoded as opcode = 05 (logical-XNOR operation), [RA] = 0x04, [RB] = 0x05 which produces the output result as [RD] = 0xFFFFFFFA. The processor has produced an erroneous output in both the cases, which is indicated by fault_online = 1. These faults may be caused either by permanent defects or by SEU induced temporary faults or by any other kind of soft errors.

Figure  8.  (Color online) Simulation results of self-testable DLX RISC processor (faulty case).
DownLoad: Full-Size Img PowerPoint
Figure  7.  (Color online) Simulation results of Self-testable DLX RISC Processor (Fault-free case).
DownLoad: Full-Size Img PowerPoint

Two versions of the processor (i) standard DLX RISC architecture and (ii) TSC based Self-testable DLX RISC Processor are synthesized and implemented in 7-series Zynq FPGA (xc7z020clg484-1). The device utilization reports and overall power consumption for the two designs is summarized in Table 2. The last column in the table shows the hardware/power overhead required for the design (2), which can be traded-off with its ability to facilitate on-line concurrent self-testing.

Table  2.  Comparison of device utilization summary.
Logic resources Design 1 (Standard DLX RISC processor) Design 2 (TSC based self-testable
DLX RISC processor) 		Percentage of overhead
Utilized Available Percentage of
utilization 		Utilized Available Percentage of
utilization
1. Slice logic (LUTs) 274 53 200 0.42 552 53 200 1.04 148
2. LUT as logic 226 53 200 0.42 504 53 200 0.95 126
3. LUT as memory 48 17 400 0.28 48 17 400 0.28 0
4. Slice registers as FFs 155 106 400 0.15 157 106 400 0.15 0
5. DSPs 3 220 1.36 3 220 1.36 0
6. No. of bonded IOBs 58 200 29 59 299 29.50 2
7. Total power consumption 34.527 W 38.115 W 10
DownLoad: CSV  | Show Table

The Berger code provides a unidirectional error detecting capability of detecting single or multi-bit errors in a given information sequence. Berger code prediction for the various arithmetic and logical operations that are carried out by a processor ALU has been summarized in this paper. The Berger code based totally self-checking checker (TSC) combined with a two-rail checker provides a solution for the on-line detection of SEU induced temporary faults and soft errors. The work presented in this paper has demonstrated the concurrent self-testing capability of the DLX RISC processor. The implementation results obtained in this work show that the concurrent built-in self-testing capability can be incorporated in the processor design with meager overheads in the hardware (LUTs) and marginally increased power consumption.



[1]
Binu D, Kariyappa B S. A survey on fault diagnosis of analog circuits: taxonomy and state of the art. Int J Electron Commun, 2017, 73: 68 doi: 10.1016/j.aeue.2017.01.002
[2]
Constantinescu C. Intermittent faults in VLSI circuits. Proceedings of the IEEE Workshop on Silicon Errors in Logic - System Effects, 2007
[3]
Blough D M, Sullivan G F, Masson G M. Intermittent fault diagnosis in multiprocessor systems. IEEE Trans Comput, 1992, 41(11): 1430 doi: 10.1109/12.177313
[4]
Borkar S. Microarchitecture and design challenges for gigascale integration. Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture, Portland, Oregon, 2004
[5]
Constantinescu C. Trends and challenges in VLSI circuit reliability. IEEE Micro, 2003, 23(4): 14 doi: 10.1109/MM.2003.1225959
[6]
Contant O, Lafortune S D. Diagnosis of intermittent faults. Discrete Event Dynamic Systems, 2004, 14(2): 171 doi: 10.1023/B:DISC.0000018570.20941.d2
[7]
ElAarag H. A complete design of a RISC processor for pedagogical purposes. J Comput Sci Colleg, 2009, 25(2): 205
[8]
Ravi S, Joseph M. FPGA implementation of low power self testable MIPS processor. Am-Eur J Sci Res, 2017, 12(3): 135
[9]
Acharya G P, Rani M A. Design of online self-testable multi-core system using dynamic partial reconfiguration of FPGA. Int J Appl Eng Res, 2017, 12(24): 15261
[10]
Psarakis M, Gizopoulos D, Sanchez E. Microprocessor software-based self-testing. IEEE Design & Test of Computers, 2010: 4
[11]
Wen C H P, Wang L C. Simulation- based functional test generation for embedded processors. IEEE Trans Comput, 2006, 55(11): 1335 doi: 10.1109/TC.2006.186
[12]
Kranitis N, Paschalis A, Gizopoulos D. Software-based self-testing of embedded processors. IEEE Trans Comput, 2005, 54(4): 461 doi: 10.1109/TC.2005.68
[13]
Psarakis M, Gizopoulos D, Hatzimihail M. Systematic software-based self- test for pipelined processors. IEEE Trans Very Large Scale Integr Syst, 2008, 16(11): 1441 doi: 10.1109/TVLSI.2008.2000866
[14]
Batcher K, Papachristou C. Instruction randomization self-test for processor cores. Proc 17th IEEE VLSI Test Symposium, 1999: 34.
[15]
Gizopoulos D, Paschalis A, Zorian Y. Embedded processor-based self-test. Kluwer Academic Publishers, 2013
[16]
Lo J, Thanawastien S, Rao T R N. Concurrent error correction in arithemetic and logical operations using Berger codes. Proceedings of the 9th Symposium on Computer Arithmetic, Santa Monica, CA, 1989: 233
[17]
Kavousianos X, Nikolos D, Foukarakis G. New efficient totally Self-checking Berger code checkers. Integration, the VLSI Journal, 1999, 28: 101 doi: 10.1016/S0167-9260(99)00013-9
[18]
Lala P K. Fault tolerant and fault testable hardware design. Prentice-Hall International, 1985
[19]
Lala P K. Self-checking and fault-tolerant digital design. Morgan Kaufmann, 2001
Fig. 1.  Architecture of DLX RISC processor.

DownLoad: Full-Size Img PowerPoint
Fig. 2.  Five stage pipelining of DLX processor.

DownLoad: Full-Size Img PowerPoint
Fig. 3.  (Color online) Processor model for software-based self-testing.

DownLoad: Full-Size Img PowerPoint
Fig. 4.  Simplified architecture of proposed self-testable DLX processor.

DownLoad: Full-Size Img PowerPoint
Fig. 5.  (a) Self-checking 2-rail checker. (b) Self-checking 2-rail checker with 6 inputs.

DownLoad: Full-Size Img PowerPoint
Fig. 6.  4 × 4 binary array multiplier.

DownLoad: Full-Size Img PowerPoint
Fig. 8.  (Color online) Simulation results of self-testable DLX RISC processor (faulty case).

DownLoad: Full-Size Img PowerPoint
Fig. 7.  (Color online) Simulation results of Self-testable DLX RISC Processor (Fault-free case).

DownLoad: Full-Size Img PowerPoint

Table 1.   Instruction formats of DLX RISC

Instruction type bits
31–26 25–21 20–16 15–11 10–0
R-type Opcode R1 R2 Rd Unused
I-type Opcode R1 R2 Immediate
J-type Opcode Operand value
DownLoad: CSV

Table 2.   Comparison of device utilization summary.

Logic resources Design 1 (Standard DLX RISC processor) Design 2 (TSC based self-testable
DLX RISC processor) 		Percentage of overhead
Utilized Available Percentage of
utilization 		Utilized Available Percentage of
utilization
1. Slice logic (LUTs) 274 53 200 0.42 552 53 200 1.04 148
2. LUT as logic 226 53 200 0.42 504 53 200 0.95 126
3. LUT as memory 48 17 400 0.28 48 17 400 0.28 0
4. Slice registers as FFs 155 106 400 0.15 157 106 400 0.15 0
5. DSPs 3 220 1.36 3 220 1.36 0
6. No. of bonded IOBs 58 200 29 59 299 29.50 2
7. Total power consumption 34.527 W 38.115 W 10
DownLoad: CSV
[1]
Binu D, Kariyappa B S. A survey on fault diagnosis of analog circuits: taxonomy and state of the art. Int J Electron Commun, 2017, 73: 68 doi: 10.1016/j.aeue.2017.01.002
[2]
Constantinescu C. Intermittent faults in VLSI circuits. Proceedings of the IEEE Workshop on Silicon Errors in Logic - System Effects, 2007
[3]
Blough D M, Sullivan G F, Masson G M. Intermittent fault diagnosis in multiprocessor systems. IEEE Trans Comput, 1992, 41(11): 1430 doi: 10.1109/12.177313
[4]
Borkar S. Microarchitecture and design challenges for gigascale integration. Proceedings of the 37th annual IEEE/ACM International Symposium on Microarchitecture, Portland, Oregon, 2004
[5]
Constantinescu C. Trends and challenges in VLSI circuit reliability. IEEE Micro, 2003, 23(4): 14 doi: 10.1109/MM.2003.1225959
[6]
Contant O, Lafortune S D. Diagnosis of intermittent faults. Discrete Event Dynamic Systems, 2004, 14(2): 171 doi: 10.1023/B:DISC.0000018570.20941.d2
[7]
ElAarag H. A complete design of a RISC processor for pedagogical purposes. J Comput Sci Colleg, 2009, 25(2): 205
[8]
Ravi S, Joseph M. FPGA implementation of low power self testable MIPS processor. Am-Eur J Sci Res, 2017, 12(3): 135
[9]
Acharya G P, Rani M A. Design of online self-testable multi-core system using dynamic partial reconfiguration of FPGA. Int J Appl Eng Res, 2017, 12(24): 15261
[10]
Psarakis M, Gizopoulos D, Sanchez E. Microprocessor software-based self-testing. IEEE Design & Test of Computers, 2010: 4
[11]
Wen C H P, Wang L C. Simulation- based functional test generation for embedded processors. IEEE Trans Comput, 2006, 55(11): 1335 doi: 10.1109/TC.2006.186
[12]
Kranitis N, Paschalis A, Gizopoulos D. Software-based self-testing of embedded processors. IEEE Trans Comput, 2005, 54(4): 461 doi: 10.1109/TC.2005.68
[13]
Psarakis M, Gizopoulos D, Hatzimihail M. Systematic software-based self- test for pipelined processors. IEEE Trans Very Large Scale Integr Syst, 2008, 16(11): 1441 doi: 10.1109/TVLSI.2008.2000866
[14]
Batcher K, Papachristou C. Instruction randomization self-test for processor cores. Proc 17th IEEE VLSI Test Symposium, 1999: 34.
[15]
Gizopoulos D, Paschalis A, Zorian Y. Embedded processor-based self-test. Kluwer Academic Publishers, 2013
[16]
Lo J, Thanawastien S, Rao T R N. Concurrent error correction in arithemetic and logical operations using Berger codes. Proceedings of the 9th Symposium on Computer Arithmetic, Santa Monica, CA, 1989: 233
[17]
Kavousianos X, Nikolos D, Foukarakis G. New efficient totally Self-checking Berger code checkers. Integration, the VLSI Journal, 1999, 28: 101 doi: 10.1016/S0167-9260(99)00013-9
[18]
Lala P K. Fault tolerant and fault testable hardware design. Prentice-Hall International, 1985
[19]
Lala P K. Self-checking and fault-tolerant digital design. Morgan Kaufmann, 2001
1

Simulation study on single event burnout in linear doping buffer layer engineered power VDMOSFET

Jia Yunpeng, Su Hongyuan, Jin Rui, Hu Dongqing, Wu Yu, et al.

Journal of Semiconductors, 2016, 37(2): 024008. doi: 10.1088/1674-4926/37/2/024008
2

Experimental study on the single event effects in pulse width modulators by laser testing

Wen Zhao, Xiaoqiang Guo, Wei Chen, Hongxia Guo, Dongsheng Lin, et al.

Journal of Semiconductors, 2015, 36(11): 115008. doi: 10.1088/1674-4926/36/11/115008
3

Impacts of test factors on heavy ion single event multiple-cell upsets in nanometer-scale SRAM

Yinhong Luo, Fengqi Zhang, Hongxia Guo, Yao Xiao, Wen Zhao, et al.

Journal of Semiconductors, 2015, 36(11): 114009. doi: 10.1088/1674-4926/36/11/114009
4

Single event soft error in advanced integrated circuit

Yuanfu Zhao, Suge Yue, Xinyuan Zhao, Shijin Lu, Qiang Bian, et al.

Journal of Semiconductors, 2015, 36(11): 111001. doi: 10.1088/1674-4926/36/11/111001
5

Multi-bit upset aware hybrid error-correction for cache in embedded processors

Jiaqi Dong, Keni Qiu, Weigong Zhang, Jing Wang, Zhenzhen Wang, et al.

Journal of Semiconductors, 2015, 36(11): 114006. doi: 10.1088/1674-4926/36/11/114006
6

Analytical modeling and simulation of germanium single gate silicon on insulator TFET

T. S. Arun Samuel, N. B. Balamurugan

Journal of Semiconductors, 2014, 35(3): 034002. doi: 10.1088/1674-4926/35/3/034002
7

Impact of temperature on single event upset measurement by heavy ions in SRAM devices

Tianqi Liu, Chao Geng, Zhangang Zhang, Fazhan Zhao, Song Gu, et al.

Journal of Semiconductors, 2014, 35(8): 084008. doi: 10.1088/1674-4926/35/8/084008
8

A voltage regulator system with dynamic bandwidth boosting for passive UHF RFID transponders

Jinpeng Shen, Xin'an Wang, Shan Liu, Shoucheng Li, Zhengkun Ruan, et al.

Journal of Semiconductors, 2013, 34(10): 105004. doi: 10.1088/1674-4926/34/10/105004
9

Stacking fault energy in some single crystals

Aditya M.Vora

Journal of Semiconductors, 2012, 33(6): 062001. doi: 10.1088/1674-4926/33/6/062001
10

An SEU-hardened latch with a triple-interlocked structure

Li Yuanqing, Yao Suying, Xu Jiangtao, Gao Jing

Journal of Semiconductors, 2012, 33(8): 085002. doi: 10.1088/1674-4926/33/8/085002
11

SRAM single event upset calculation and test using protons in the secondary beam in the BEPC

Wang Yuanming, Guo Hongxia, Zhang Fengqi, Zhang Keying, Chen Wei, et al.

Journal of Semiconductors, 2011, 32(9): 092001. doi: 10.1088/1674-4926/32/9/092001
12

30-GHz millimeter-wave carrier generation with single sideband modulation based on stimulated Brillouin scattering

Luo Zhen'ao, Xie Liang, Qi Xiaoqiong, Wang Hui

Journal of Semiconductors, 2011, 32(9): 092004. doi: 10.1088/1674-4926/32/9/092004
13

First-principle study on anatase TiO2 codoped with nitrogen and ytterbium

Gao Pan, Zhang Xuejun, Zhou Wenfang, Wu Jing, Liu Qingju, et al.

Journal of Semiconductors, 2010, 31(3): 032001. doi: 10.1088/1674-4926/31/3/032001
14

Thermal analysis and test for single concentrator solar cells

Cui Min, Chen Nuofu, Yang Xiaoli, Wang Yu, Bai Yiming, et al.

Journal of Semiconductors, 2009, 30(4): 044011. doi: 10.1088/1674-4926/30/4/044011
15

Modeling and analysis of single-event transients in charge pumps

Zhao Zhenyu, Li Junfeng, Zhang Minxuan, Li Shaoqing

Journal of Semiconductors, 2009, 30(5): 055006. doi: 10.1088/1674-4926/30/5/055006
16

Testing content addressable memories with physical fault models

Ma Lin, Yang Xu, Zhong Shiqiang, Chen Yunji

Journal of Semiconductors, 2009, 30(8): 085001. doi: 10.1088/1674-4926/30/8/085001
17

A Failure-Mechanism Identification Method in Accelerated Testing

Guo Chunsheng, Xie Xuesong, Ma Weidong, Cheng Yaohai, Li Zhiguo, et al.

Chinese Journal of Semiconductors , 2006, 27(3): 560-563.

18

Full-Chip Scalable Routing Framework Considering Congestion and Performance

Yao Hailong, Cai Yici, Hong Xianlong, Zhou Qiang

Chinese Journal of Semiconductors , 2006, 27(7): 1201-1208.

19

Temperature Dependence of Vacuum Rabi Splitting in a Single Quantum Dot-Semiconductor Microcavity

Zhu Kadi, Li Waisang

Chinese Journal of Semiconductors , 2006, 27(3): 489-493.

20

Design, Fabrication, and Testing of Single-Side Alignment of 16×0.8nm Arrayed Waveguide Grating

Li Jian, An Junming, Wang Hongjie, Xia Junlei, Hu Xiongwei, et al.

Chinese Journal of Semiconductors , 2005, 26(2): 254-257.

1. Abdi, A., Shahoveisi, S. FT-EALU: fault-tolerant arithmetic and logic unit for critical embedded and real-time systems. Journal of Supercomputing, 2023, 79(1): 626-649. doi:10.1007/s11227-022-04698-8
2. Acharya, G.P., Rani, M.A., Kumar, G.G. et al. Adaptation of March-SS algorithm to word-oriented memory built-in self-test and repair. Indonesian Journal of Electrical Engineering and Computer Science, 2022, 26(1): 96-104. doi:10.11591/ijeecs.v26.i1.pp96-104
3. Tian, W., Li, C., Liu, K. et al. Fabrication of Transferable and Micro/Nanostructured Superhydrophobic Surfaces Using Demolding and iCVD Processes. ACS Applied Materials and Interfaces, 2022. doi:10.1021/acsami.2c17613
4. Chlaab, A.K., Flayyih, W.N., Rokhani, F.Z. Lightweight hamming product code based multiple bit error correction coding scheme using shared resources for on chip interconnects. Bulletin of Electrical Engineering and Informatics, 2020, 9(5): 1979-1989. doi:10.11591/eei.v9i5.1876
5. Mohammadi, S., Omidi, R., Lotfinejad, M. Low-Power Area-Efficient Fault Tolerant Adder in Current Mode Multi Valued Logic Using Berger Codes. Journal of Electronic Testing: Theory and Applications (JETTA), 2020, 36(4): 555-563. doi:10.1007/s10836-020-05887-0

    • Search

    Advanced Search >>

    GET CITATION

    G. Prasad Acharya, M. Asha Rani. Berger code based concurrent online self-testing of embedded processors[J]. Journal of Semiconductors, 2018, 39(11): 115001. doi: 10.1088/1674-4926/39/11/115001
    G P Acharya, M A Rani, Berger code based concurrent online self-testing of embedded processors[J]. J. Semicond., 2018, 39(11): 115001. doi: 10.1088/1674-4926/39/11/115001.
    shu

    Export: BibTex EndNote

    Article Metrics

    Article has an altmetric score of 1
    Article has an altmetric score of 1

    Article views: 3589 Times PDF downloads: 33 Times Cited by: 5 Times

    History

    Received: 13 January 2018 Revised: 08 May 2018 Online: Uncorrected proof: 15 June 2018Published: 01 November 2018

    Catalog

      Email This Article

      User name:
      Email:*请输入正确邮箱
      Code:*验证码错误
      Send
      Article Navigation >  Journal of Semiconductors  > 2018  >  39(11): 115001
      G. Prasad Acharya, M. Asha Rani. Berger code based concurrent online self-testing of embedded processors[J]. Journal of Semiconductors, 2018, 39(11): 115001. doi: 10.1088/1674-4926/39/11/115001 ****G P Acharya, M A Rani, Berger code based concurrent online self-testing of embedded processors[J]. J. Semicond., 2018, 39(11): 115001. doi: 10.1088/1674-4926/39/11/115001.
      Citation:
      G. Prasad Acharya, M. Asha Rani. Berger code based concurrent online self-testing of embedded processors[J]. Journal of Semiconductors, 2018, 39(11): 115001. doi: 10.1088/1674-4926/39/11/115001 ****
      G P Acharya, M A Rani, Berger code based concurrent online self-testing of embedded processors[J]. J. Semicond., 2018, 39(11): 115001. doi: 10.1088/1674-4926/39/11/115001.
      shu

      Berger code based concurrent online self-testing of embedded processors

      DOI: 10.1088/1674-4926/39/11/115001
      • 1.

        Department of ECE, Sree Nidhi Institute of Science and Technology, Hyderabad, TG, India

      • 2.

        Department of ECE, JNTUH College of Engineering, JNTUH University, Hyderabad, TG, India

      More Information
      • Corresponding author: gprasad04@gmail.com
      • Received Date: 2018-01-13
      • Revised Date: 2018-05-08
      • Published Date: 2018-11-01

      Catalog

        Journal of Semiconductors © 2017 All Rights Reserved   京ICP备05085259号-2

        /

        DownLoad:  Full-Size Img  PowerPoint
        Return
        Return