1. Introduction

As integrated circuits and semiconductor devices become smaller, the electronic equipment and components are susceptible to microwave pulses. A variety of microwave pulses can cause the failure and even destruction of electronic equipment and components^[1–9]. A lot of work has been done in the fields of electronic system damage and device damage, some of which focus on the effects of pulse parameters on device damage. Different measurements are proposed to study the effect of ultra wide bandwidth (UWB) and radar pulses on the receiver of a digital wireless communication system^[10]. The findings show that Bluetooth communication has the ability to transmit data up to the PRF of 2 kHz, while WLAN communication is able to transmit data up to the PRF of 3.5 kHz , and a high PRF and pulse lengths can make both communication links damaged. In Ref. [11], Daniel et al. provide an overview of the susceptibility of many various electronic devices, the findings demonstrate that many types of electronic equipment, including logic devices, microprocessor boards, PC networks, and microprocessor boards, are caused by electromagnetic pulse (EMP), high power microwave (HPM) pulses, and UWB. The analysis presents that a lower field strength can only damage electronic components such as transistors or diodes on the chip, while a higher amplitude is needed to destroy the band wire, multiple component, and chip wire. The Swedish Defence Authorities have searched for the effects of high power microwave radiation on the electronic systems including military equipment and civil equipment^[12]. The results manifest that the distance for the damage of HPM can reach approximately one kilometer. In addition, the pulse width and the PRF are crucial for some types of disturbance, and the first pulse of a pulse train usually leads to the permanent damage. In Ref. [13], Ma et al. injected pulsed microwaves with different PRF and duty cycles (DCs) into the output of a bipolar transistor; the results indicate that the pulses with lower PRF cannot lead to any thermal stacking within the device, and increasing the PRF can cause more accumulating temperature, in addition, they found that with rising DC the accumulating temperature falls.

Researchers pay more attention to the damage of an electronic system level caused by HPM and EMP, while fewer researchers have analysed theoretically the device damage level caused by HPM and EMP. The Darlington transistor has significant applications in power amplifier circuits, power circuits, switching circuits, drive small type relay circuits, drive LED intelligence display screen circuits, etc. Although new structures and new materials are brought up to improve the working efficiency of the Darlington transistor, less study has been carried out on the damage of the Darlington transistor induced by HPM and EMP. In this paper, a two-dimensional electron-thermal model of the silicon PNP type Darlington transistor is established using the device simulator Sentaurus-TCAD. The output-input characteristic curves are obtained firstly, then the damage effect and mechanism caused by repetitive pulse is discussed. Finally, the relationship between the heat accumulation effect caused by HPM and pulsed parameters such as PRF and DC are studied.

2. Structure and model

2.1 Device structure

The equivalent circuit of the PNP type Darlington transistor is presented in Fig. 1, E, B, and C represent the emitter, base, and collector of the device, respectively. T1 and T2 represent two PNP transistors of the same power, specially, T1 is called the first stage transistor, while T2 is defined as the second stage transistor. Fig. 2 shows the structure of the device in this paper. Since these two PNP transistors are the same, hence we just list the parameters of the T1 transistor. The horizontal width of the emitter and the base of the T1 transistor are 8 and 20 μm, respectively. P₁⁺ is the emitter region of the T1 transistor where the doping method is Gauss doping with doped impurity of the Boron element and a surface concentration of 1 × 10²⁰ cm⁻³, N₁ is the base region of the T1 transistor where the doping mode is uniform doping with doped impurity of the Phosphorus element and the doping concentration of 1 × 10¹⁷ cm⁻³. The emitter junction and the base junction of the T1 transistor are 0.4 and 0.8 μm. It is noted that the collector of the Darlington transistor is shared by the T1 and T2 transistors. P-epi is the 2-μm-thick p-type epitaxial layer with doped impurity of the Phosphorus element and the doping concentration of 5 × 10¹⁵ cm⁻³. P⁺-sub represent the 12-μm-thick collector substrate of p-type silicon with doped impurity of the Phosphorus element and the doping concentration of 5 × 10¹⁹ cm⁻³. The thermal electrode is specified at the bottom of the device (along line y = 14 μm), in which the lattice temperature is assumed to be a constant of 300 K. In addition, the sidewall boundaries (along lines x = 0 and x = 40.5 μm) and the upper surface are thermally insulated from the environment.

2.2 Numerical model

In this paper, the device simulator is used to calculate the electronic behavior of the Darlington transistor by iteratively solving the Poisson equation, the current-continuity equations^[14]. High current and high voltage generated by the injected signals would produce a huge Joule heat during the injection of the repetitive pulse, which leads to a significant temperature variation within the Darlington transistor. Considering the influence of the internal self-heating effect on the device, the heat of the equation should be calculated:

$$\begin{split}& c\frac{{\partial T}}{{\partial t}} - \nabla \cdot k\nabla T\\& = - \nabla \cdot \left[ {({P_{\rm{n}}}T + {\phi _{\rm{n}}}){{{J}}_{\rm{n}}} + ({P_{\rm{p}}}T + {\phi _{\rm{p}}}){{{J}}_{\rm{p}}}} \right] - \left( {{E_{\rm C}} + \frac{3}{2}{k_{\rm{B}}}T} \right)\nabla \cdot {{{J}}_{\rm n}}\\& \quad - \left( {{E_{\rm{V}}} - \frac{3}{2}{k_{\rm{B}}}T} \right)\nabla \cdot {{{J}}_{\rm{p}}} + qR({E_{\rm{C}}} - {E_{\rm{V}}} + 3{k_{\rm{B}}}T),\end{split}$$

(1)

in which c is the lattice heat capacity, k is the thermal conductivity, J_n and J_p are the electron and hole current density, respectively. E_C and E_V are the conduction and valence band energy, respectively, k_B denotes the Boltzmann constant and R is the recombination rate. In addition, the thermodynamic model is adopted assuming that the charge carriers are in thermal equilibrium with the lattice. SRH recombination, Auger recombination, and the Avalanche breakdown model are taken into account in generation and recombination of the charge carrier.

In this paper, the square pulse modulated sinusoidal signals with the carrier frequency of 1 GHz are used^[15], and the device is considered to have failed when the peak temperature of the device reaches the melting point of silicon (1688 K).

3. Results and discussions

3.1 Damage process under repetitive pulse

The simulation circuit is shown in Fig. 3, where the Darlington transistor is in the active mode of operation. The input-output characteristic curve of the device is obtained and plotted in Fig. 4, therefore, the quiescent DC operation point is set to V_CEQ = −6.5 V, I_CQ = −0.3 mA, V_BEQ = −1.4 V, I_BQ = −0.4 μA, and the values of V_CC, R_b, and R_c are set to −9.0 V, 19.0 MΩ, and 8.3 kΩ, respectively according to the equations below:

$${R_{\rm{b}}} = \frac{{{V_{{\rm{cc}}}} - {V_{{\rm{BEQ}}}}}}{{{I_{{\rm{BQ}}}}}},$$

(2)

$${R_{\rm{c}}} = \frac{{{V_{{\rm{cc}}}} - {V_{{\rm{CEQ}}}}}}{{{I_{{\rm{CQ}}}}}}.$$

(3)

To investigate the heat accumulation effect of the Darlington transistor caused by repetitive pulse, the square wave pulse modulated sinusoidal signals with a PRF of 10 MHz and a pulse width of 60 ns are injected into the output of the device. The frequency and the amplitude of the carrier are 1 GHz and 15 V, respectively. Fig. 5 depicts the relationship between peak temperature and simulation time within the first five cycles. As we can see from the figure the peak temperature increases within the square pulse and decreases in the pulse intervals. The peak temperature variation presents a tendency of increase–decrease, on the whole, the peak temperature rises versus the simulation time until the Darlington transistor is destroyed.

3.2 Influence of PRF on device damage

In this section, the repetitive pulse signals with a pulse width of 60 ns and different PRF from 50 kHz to 10 MHz are injected into the device. Fig. 6 shows the variation of peak temperature, ΔT, with time when PRFs are 0.1, 1, 5, and 10 MHz, respectively. ΔT is defined as the difference between the value of peak temperature at the end of the fifth period and the ambient temperature. It can be seen from Fig. 6 that with decreasing the PRF the value of ΔT is decreasing too. The value of ΔT is 81.0 K when PRF is 10 MHz, while the value of ΔT drops to 10.0 K when the PRF decreases to 1 MHz. Note that the value of ΔT is only 4.3 K at the end of every pulse when the PRF is 100 kHz, demonstrating that heat accumulation hardly exists within the Darlington transistor, that is to say, this kind of repetitive pulse cannot destroy the Darlington transistor established in this paper.

Repetitive pulse signals (pulse widths are 20, 40, 60, and 80 ns, respectively) with PRF varying from 50 kHz to 10 MHz are injected into the output of the device, and Fig. 7 presents the simulation results.

As shown in Fig. 7, for the repetitive pulse with the same pulse width, the relationship between ΔT and PRF can be divided into three parts. In the first part, the value of ΔT is a constant of 4.3 K when PRF is less than 200 kHz, which means that there has been no heat accumulation within the device in this case. In the second stage, it can be seen clearly that ΔT presents a linear relationship dependence on the PRF which varies from 200 kHz to 4 MHz. For the last part, it shows a quasi-linear relationship between ΔT and PRF when the PRF is larger than 4 MHz but smaller than 10 MHz. For instance, the piecewise function for the interference signal with a pulse width of 60 ns can be obtained:

$$\Delta T = \left\{ \begin{array}{l}4.3,\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\;\quad\;\;0 < f < 200\,\, {\mathop{\rm kHz}\nolimits}, \\{\rm{ }}1.1 \times {10^{ - 5}}f - 0.3,\;\;\;\;\;\;200 \,\, {\rm {kHz}} \leqslant f < 4\,\, {\mathop{\rm MHz}\nolimits}, \\6.4 \times {10^{ - 6}}f + 18.1,\;\;\;\;4\,\, {\mathop{\rm MHz}\nolimits} \leqslant f < 10\,\, {\mathop{\rm MHz}\nolimits}, \end{array} \right.$$

(4)

of which the correlation coefficients (R²) of the second equation and the third equation are 0.999 and 0.993 respectively, which shows high degrees of fitting. Besides, we can form a conclusion from the figure that for the pulse with the same PRF, the wider the pulse width is, the larger the value of ΔT is.

3.3 Influence of single pulse on device damage

To study the effects of the single pulse interference signal on the device damage, Fig. 8 shows the response of peak temperature versus time when single pulses with pulse widths of 20, 40, 60, and 80 ns, respectively are injected.

As we can see from Fig. 8, the duration of temperature rising is much less than that of temperature decreasing, and the peak temperature would drop to 304.3 K in approximately 4.0 μs after removing the single pulse signals, which means that there has been no heat accumulation within the Darlington transistor if the PRF is smaller than 250 kHz; this conclusion is consistent with the above analysis. For the sake of a better understanding of the relationship between the peak temperature and the time, we obtain the corresponding relations of the four rising edges:

$$\left\{ \begin{array}{l}{T_{20{\mkern 1mu} {\mkern 1mu} {\rm{ns}}}} = 296.5 + 89.0 \times \left\{ {(1 - \exp \left[ { - t/(3.0 \times {{10}^{ - 8}})} \right]} \right\}\\{T_{40\,\,{\rm{ns}}}} = 296.1 + 76.4 \times \left\{ {(1 - \exp \left[ {- t/(2.4 \times {10^{ - 8}})} \right]} \right\}\\{T_{60\,\,{\rm{ns}}}} = 297.2 + 81.2 \times \left\{ {(1 - \exp\left[ {- t/(2.8 \times {10^{ - 8}})} \right]} \right\}\\{T_{80\,\,{\rm{ns}}}} = 298.4 + 85.0 \times \left\{ {(1 - \exp\left[ {- t/(3.2 \times {10^{ - 8}})} \right]} \right\}\end{array} \right.,$$

(5)

where R² are 0.982, 0.993, 0.995, and 0.996, respectively, presenting good degrees of fitting. For the different falling edges, the curves with four various pulse widths are also fitted and expressed as:

$$\left\{ \begin{array}{l}{T_{20\,\,{\rm{ns}}}} = 304.3 + 39.4 \times \exp [ - t/(8.0 \times {10^{ - 8}})]\\{T_{40\,\,{\rm{ns}}}} = 304.3 + 67.7 \times \exp [ - t/(1.3 \times {10^{ - 7}})]\\{T_{60\,\,{\rm{ns}}}} = 304.3 + 91.2 \times \exp [ - t/(1.5 \times {10^{ - 7}})]\\{T_{80\,\,{\rm{ns}}}} = 304.3 + 111.7 \times \exp [ - t/(1.8 \times {10^{ - 7}})]\end{array} \right.,$$

(6)

of which R² are 0.993, 0.995, 0.996, and 0.997, respectively, showing good degrees of fitting. It can be found that both rising edges and falling edges obey abnormal exponential progression. For curves of falling edge, the equations all comply with the rules:

$$T = A + B(T) \times \exp ( - t/{\tau _{{\rm{th}}}}),$$

(7)

where A is a constant of 304.3 K, and B(T) is a constant connected with the temperature of the device. For the constant of τ_th, it is a function of temperature^[16], the initial temperatures of the falling edge are different for different pulse widths, hence the values of τ_th are different for different pulse widths, too. According to this equation, we can predict the temperature variation within the Darlington transistor under the injections of single pulses with different pulse widths.

3.4 Influence of duty cycle on device damage

The influence of duty cycle on the peak temperature variation is studied because DC is a significant parameter of a repetitive pulse. The schematic diagram of the simulation circuit is shown in Fig. 3. The interference signals with an average power of 1.2 × 10³ W and a PRF of 5 MHz are injected into the Darlington transistor from the output, and the DC of the repetitive pulse varies from 0.025 to 0.175. Fig. 9 depicts the relationship between ΔT and DC, as we can see from this figure that the value of ΔT significantly falls as DC rises. The value of ΔT is 149.0 K when DC is 0.025, while it drops to 3.2 K when DC is 0.175. In addition, we can clearly see that there is little temperature accumulation (approximately 3.0 K) when DC is lower than 0.15.

Temperature elevation occurs in the positive half-period of the sinusoidal signal and the damage location is in the cylindrical region of the base-emitter junction of the T2 transistor. The variations of electric field (E) as a function of the x axis (along the line y = 0.3 μm), with the repetitive pulse with different duty cycles injected at the moment of 4.75 ns, is shown in Fig. 10. With increasing duty cycle, the value of E at the position of x = 32.5 μm (damage position) is decreasing. The value of E (1.1 × 10⁶ V/cm) with DC = 0.025 is approximately two times larger than that of E (5.1 × 10⁵ V/cm) with DC = 0.175. The mean power is proportional to DC and the square of the voltage:

$$P \propto {\rm DC} \cdot U_0^2.$$

(8)

Because the average power is a definite value, the larger the DC is, the smaller the U₀ is. As we know, the value of E is proportional to U₀, in other words, the value of E which is at the position of x = 32.5 μm decreases with the decreases of the U₀. Through the above analysis in theory, we can make a conclusion that the larger the DC is, the smaller the value of E at the damage position is, which is consistent with the simulation results presented in Fig. 10 at the moment of 4.75 ns for different duty cycles (along the line y = 0.3 μm).

Fig. 11(a) shows the current density (J) across the damage location (along the line y = 0.3 μm) at 4.75 ns. From Fig. 11(a), it can be seen that with decreasing duty cycle the value of J, which is at the damage position, increases. We know that the value of U₀ increases as DC decreases, and a higher voltage causes a larger current density at the position of x = 32.5 μm. In addition, the figure shows that the values of the current density at the damage position are almost equal to zero when DC is larger than 0.125, the reason is that a voltage less than a certain value cannot produce a high current for the Darlington transistor in this paper.

The instantaneous power density (P) across the damage location (along the line y = 0.3 μm) at 4.75 ns is presented in Fig. 11(b). P is defined as the product of the electric field E and the current density J. As Fig. 11(b) shows, firstly, the value of P decreases at the damage position of x = 32.5 μm with the rise of DC. P is approximately 5.1 × 10¹² W/cm³ when DC is 0.025, however, when DC increases to 0.125, P is only about 5.8 × 10⁸ W/cm³. Secondly, the value of P is so small at the damage position that it can be negligible when DC is larger than 0.125. Therefore, this conclusion can account for the phenomenon that temperature variation ΔT in the damage position is small when the Darlington transistor is injected into a repetitive pulse with a DC of higher than 0.125.

4. Conclusion

In this paper, we established a two-dimensional electron-thermal model of the silicon PNP type Darlington transistor utilizing the device simulator. Firstly, the damage effect of the device which is induced by the repetitive pulse signals with different PRFs and duty cycles is investigated. The results demonstrate that the temperature variation has a periodic rule of decrease-increase. For the repetitive pulse with the same pulse width, with PRF increases the value of temperature variation increases; while for the repetitive pulse with the same PRF, the larger the value of pulse width is, the higher the value of temperature variation is. Secondly, the damage laws of the device caused by a single pulse with pulse width from 20 to 80 ns are obtained, which shows that there is little temperature accumulation within the device when PRF is lower than approximately 200 kHz , in other words, the Darlington transistor will not be destroyed by the interference signals if the device is not destroyed in the first pulse of a pulse train in this case. Finally, the effect of DC on temperature variation is studied. The result presents that temperature variation decreases with the DC rises. The reason for this result is that the values of electronic field E and the current J density at the damage position fall as the DC rises, which leads to the value of power density P decreasing with the DC increasing. The conclusions obtained from this paper can predict the damage effect of the Darlington transistor caused by some specific pulse interference signals.