1. Introduction

Bandgap reference (BGR) circuits are essential blocks for high voltage gate driver integrated circuits (HVIC), and the voltage accuracy plays a significant role in determining the performance of all subsequent circuits which depend on an accurate and stable reference^{[1, 2]}. Any variations in the reference voltage will directly affect the performance of the overall system. Since the HVICs work under the wider temperature range, developing a temperature-compensated reference is crucial.

In order to achieve high-precision CMOS reference, several curvature compensation techniques have been developed in Refs. [3–8]. The piecewise-linear curvature-compensation technique has been proposed in Refs. [3–6]. In these approaches, a nonlinear curvature-corrected current is generated and added to the output of a first-order BGR when the operating temperature is higher than a pre-determined value, but the accuracy is limited at a wider temperature range. In Ref. [7], high-order nonlinearities are cancelled by incorporating two different types of resistors with opposite TC. However, intensive trimming is needed to match the resistor ratios, which will increase the circuit complexity and cost. The multiple temperature trimming technique in Ref. [8] achieves high precision performance but is not favored because of its complicated circuit implementation.

In this paper, we propose a novel temperature compensating method for canceling high-order nonlinearities by using the voltage difference of MOS transistors operating in a saturate region to compensate the nonlinearities of base-emitter voltage of the bipolar transistor (V_BE). The PSRR are enhanced by employing a novel voltage pre-regulator circuit to suppress the supply noise over a broad frequency range, which costs low headroom and thus the circuit can operate in a broad supply voltage range.

2. Conventional bandgap reference

In a conventional bandgap reference circuit, as shown in Fig. 1, the op-amp and current mirror (M1 and M2) forces nodes V1 and V2 to be at the same potential, thus generating the desired current I_CTAT through R₂ (R₁ = R₂) and I_PTAT through R₃ and Q2. V_ref is generated by the sum of I_PTAT and I_CTAT multiplied by the output resistor R₄.

$${I_{{\rm{PTAT}}}} = \frac{{\Delta {V_{{\rm{BE}}}}}}{{{R_3}}},$$

(1)

$${I_{{\rm{CTAT}}}} = \frac{{{V_{{\rm{BE}}}}}}{{{R_2}}},$$

(2)

$${V_{{\rm{ref}}}} = ({I_{{\rm{CTAT}}}} + {I_{{\rm{PTAT}}}}){R_4} = \left(\frac{{{V_{{\rm{BE}}}}}}{{{R_2}}} + \frac{{\Delta {V_{{\rm{BE}}}}}}{{{R_3}}}\right){R_4}.$$

(3)

The difference in base-emitter voltage between Q1 and Q2 (ΔV_BE) can be written as:

$$\Delta {V_{{\rm{BE}}}} = {V_{\rm{T}}}\ln N = \frac{{kT}}{q}\ln N ,$$

(4)

where V_T is the thermal voltage, N is the emitter-area ratio of Q2 and Q1, T is the actual working temperature, k is Boltzmann constant, and q is the charge of an electron. We can conclude that the current I_PTAT generated by ΔV_BE across the resistor is linear with temperature from Eqs. (1) and (4).

The base–emitter voltage of the bipolar transistor (V_BE) can be expressed as^{[9, 10]}:

$${V_{{\rm{BE}}}} = {V_{{\rm{g}}0}} - \frac{T}{{{T_0}}}\left( {{V_{{\rm{g}}0}} - {V_{{\rm{BE}}0}}} \right) - \left( {\eta - \delta } \right){V_{\rm{T}}}\ln {\frac{T}{{{T_0}}}},$$

(5)

where V_g0 is the bandgap voltage of the silicon at 0 K, the value of it is about 1.2 V, T is the actual working temperature, T₀ is specified reference temperature, V_BE0 represents the base–emitter voltage of the bipolar transistor (V_BE) at T₀, η is the process related parameter with value ranging from 3.6 to 4 and δ is the order of the temperature dependence of the collector current. If the collector current is PTAT (proportional to absolute temperature), we substitute δ = 1 and if the collector current is temperature independent we substitute δ = 0^[9]. Since the collector current is PTAT in most BGRs, the value of δ in Eq. (5) is 1. V_T is equal to thermal voltage kT/q, k is Boltzmann's constant, and q is the charge of an electron. The V_Tln(T/T₀) item demonstrates a high-order nonlinearity of V_BE, which should be reduced. Transforming V_T we can obtain the following equation:

$${V_{\rm{T}}} = \frac{{kT}}{q} \Rightarrow \frac{{{V_{\rm{T}}}}}{T} = \frac{{{V_{{{\rm T}0}}}}}{{{T_0}}} \Rightarrow {V_{\rm{T}}} = \frac{{{V_{{{\rm T}0}}}}}{{{T_0}}}T,$$

(6)

where V_T0 represents the thermal voltage at T₀. Substituting Eq. (6) in Eq. (5) and using a Taylor series expansion in Eq. (5), V_BE can be rewritten in the form of:

$$\begin{split}{V_{{\rm{BE}}}}\left( T \right) = \,\, & {V_{{\rm{BE}}0}} - \frac{{{V_{{\rm{g}}0}} - {V_{{\rm{BE}}0}} + \left( {\eta - \delta } \right){V_{{\rm{T}}0}}}}{{{T_0}1!}}\left( {T - {T_0}} \right) \\& -\frac{{\left( {\eta - \delta } \right){V_{{\rm{T}}0}}}}{{{T_0}^22!}}{\left( {T - {T_0}} \right)^2} + \frac{{\left( {\eta - \delta } \right){V_{{\rm{T}}0}}}}{{{T_0}^33!}}{\left( {T - {T_0}} \right)^3} + \cdot \cdot \cdot .\end{split}$$

(7)

From Eqs. (2) and (7), we can conclude that the current I_CTAT generated by V_BE across the resistor has many nonlinear terms. A conventional bandgap reference circuit uses ΔV_BE to cancel the linear item of V_BE. However, from Eq. (7) and Eq. (4) we can see that V_BE contains many high-order items while ΔV_BE is linear with T, thus such a method only compensates for only the linear parts of V_BE while the remaining nonlinearities, second up to higher order items, still exist. These high-order items limit the accuracy of V_ref.

3. Proposed bandgap reference circuit

3.1 Compensation of nonlinearities

As previously mentioned in Section 2, I_CTAT generated by V_BE across the resistor has many nonlinear terms while I_PTAT generated by ΔV_BE across the resistor is linear with temperature. In order to compensate the nonlinearities of I_CTAT, a nonlinear current I_NL which is generated by ΔV_GS across the resistor is proposed in this paper. Combine I_CTAT, I_PTAT and I_NL, the high-order nonlinear terms of I_CTAT can be well compensated to achieve high-order curvature compensation. The compensation method of the proposed BGR core circuit is illustrated in Fig. 2.

As shown in Fig. 3, the gate source voltage of two MOS transistors operating in a saturated region can be written as follows:

$${V_{{\rm{GS}}1}} = \sqrt {\frac{{2{I_1}}}{{{\mu _{\rm{n}}}{C_{{\rm{ox}}}}\left( {W/L} \right)}}} + {V_{{\rm{th}}}},$$

(8)

$${V_{{\rm{GS}}2}} = \sqrt {\frac{{2{I_2}}}{{{\mu _{\rm{n}}}{C_{{\rm{ox}}}}\left( {K \times W/L} \right)}}} + {V_{{\rm{th}}}},$$

(9)

where I₁ and I₂ are bias current flow through transistor M1 and M2 respectively, W and L are the channel width and channel length of M1 respectively, K is the ratio of the W/L of M2 and M1, μ_n represents n-type carrier mobility and it is negative related to temperature. Let I₁ = I₂ = I = k₁T^m, μ_n = k₂T⁻ⁿ, k₁ and k₂ are parameters independent of temperature, m and n are temperature-independent numbers and values of them are about 1.5. Subtracting V_GS2 from V_GS1 gives the following expression:

$$\begin{split}\Delta {V_{{\rm{GS}}}} & = {V_{{\rm{GS}}1}} - {V_{{\rm{GS}}2}} = \sqrt {\frac{{2I}}{{{\mu _{\rm{n}}}{C_{{\rm{ox}}}}\left( {W/L} \right)}}} \left( {1 - \sqrt {\frac{1}{K}} } \right)\\& = \sqrt {\frac{{2{k_1}}}{{{k_2}{C_{{\rm{ox}}}}\left( {W/L} \right)}}} \left( {1 - \sqrt {\frac{1}{K}} } \right){T^{\frac{{m + n}}{2}}}.\end{split}$$

(10)

Since the value of m + n is between 2 and 4, the voltage ΔV_GS is positively correlated to temperature. The first order, second order and third order derivative of voltage ΔV_GS can be expressed in the following form respectively:

$$\frac{{{\rm d}\Delta {V_{{\rm{GS}}}}}}{{\rm d}T} = {k_3}\frac{{m + n}}{2}{T^{\frac{{m + n - 2}}{2}}} > 0,$$

(11)

$$\frac{{{{\rm d}^2}\Delta {V_{{\rm{GS}}}}}}{{{\rm d}{T^2}}} = {k_3}\frac{{m + n}}{2}\frac{{m + n - 2}}{2}{T^{\frac{{m + n - 4}}{2}}} > 0,$$

(12)

$$\frac{{{{\rm d}^3}\Delta {V_{{\rm{GS}}}}}}{{{\rm d}{T^3}}} = {k_3}\frac{{m + n}}{2}\frac{{m + n - 2}}{2}\frac{{m + n - 4}}{2}{T^{\frac{{m + n - 4}}{2}}} < 0,$$

(13)

$${k_3} = \sqrt {\frac{{2{k_1}}}{{{k_2}{C_{{\rm{ox}}}}\left( {W/L} \right)}}} \left( {1 - \sqrt {\frac{1}{K}} } \right).$$

(14)

Using a Taylor expansion for ΔV_GS we can obtain equation:

$$\Delta {V_{{\rm{GS}}}} = {a_0} + \frac{{{a_1}}}{{1!}}\left( {T - {T_0}} \right) + \frac{{{a_2}}}{{2!}}{\left( {T - {T_0}} \right)^2} + \frac{{{a_3}}}{{3!}}{\left( {T - {T_0}} \right)^3} + \cdots,$$

(15)

$${a_0} = {\left. {\Delta {V_{{\rm{GS}}}}} \right|_{T = {T_0}}},$$

(16)

$${a_1} = {\left. {\frac{{{\rm d}\Delta {V_{{\rm{GS}}}}}}{{\rm d}T}} \right|_{T = {T_0}}},$$

(17)

$${a_2} = {\left. {\frac{{{{\rm d}^2}\Delta {V_{{\rm{GS}}}}}}{{{\rm d}{T^2}}}} \right|_{T = {T_0}}},$$

(18)

$${a_3} = {\left. {\frac{{{{\rm d}^3}\Delta {V_{{\rm{GS}}}}}}{{{\rm d}{T^3}}}} \right|_{T = {T_0}}}.$$

(19)

Compared with the Taylor expansion for voltage V_BE in Eq. (7), it is concluded that the coefficients of Taylor expansion of V_BE and ΔV_GS are opposite. As a result, voltage ΔV_GS can cancel the second-order item of voltage V_BE completely and offset the third-order item and higher-items of voltage V_BE in some degree.

3.2 Voltage pre-regulator circuit

In this paper, a voltage pre-regulator circuit is introduced as a local supply voltage of a bandgap core circuit to boost the supply voltage suppression performance. The pre-regulated voltage should be less sensitive to the power supply and temperature because any variations in the pre-regulated voltage will directly affect the performance of the subsequent bandgap core circuit.

A simplified circuit topology of the voltage pre-regulator circuit is illustrated in Fig. 4. It consists of a reference generator, an operational amplifier, a MOS transistor M1, two resistors R₁ and R₂ and a bandgap reference core circuit. The op-amp, M1, R₁ and R₂ constitute a negative feedback loop to regulate the pre-regulated voltage V_reg. When the voltage V_reg rises, the potential of node V_F increases as well, thus the output voltage of op-amp V₁ increases. Then the voltage V_reg decreases since M1 is a common-sense amplifier. Finally, the voltage V_reg will stabilize near a fixed voltage value. The op-amp forces nodes V_ref1 and V_F to be at the same potential, so the pre-regulated voltage can be expressed as:

$${V_{{\rm{reg}}}} = \left( {1 + \frac{{{R_1}}}{{{R_2}}}} \right){V_{{\rm{ref}}1}}.$$

(20)

The reference voltage V_ref1 is generated by a first-order temperature compensated reference voltage generator and it is approximately independent of temperature. The voltage V_ref1 is given by:

$$\begin{split}{V_{{\rm{ref}}1}}& = {I_{\rm{b}}} {R_3} + {V_{{\rm{GS}}3}} = \Delta {V_{{\rm{GS}}3,2}} + {V_{{\rm{GS}}3}} \\& =\sqrt {\frac{{2{I_{\rm{b}}}}}{{{\mu _{\rm{n}}}{C_{{\rm{ox}}}}\left( {W/L} \right)}}} \left( {2 - \frac{1}{{\sqrt k }}} \right) + {V_{{\rm{TH}}0}} - {k_{{\rm{th}}}}\left( {T - {T_0}} \right),\!\!\!\!\end{split}$$

(21)

where W and L are the channel width and channel length of M3 respectively, k is the ratio of the W/L of M2 and M3, μ_n represents n-type carrier mobility and it is negative related to temperature, V_TH0 represents the V_TH voltage at the temperature T₀, k_th represents the temperature coefficient of the opening voltage V_TH, T₀ is the specified reference temperature, and T is the actual working temperature. Let I_b = k_bT^m, μ_n = k_uT⁻ⁿ, k_b and k_u be parameters independent of temperature, m and n are temperature-independent numbers and the values of them are about 1.5. Substituting I_b and μ_n in Eq. (21) and the first order derivative of voltage V_ref1 can be written as:

$$\frac{{{\rm d}{V_{{\rm{ref}}1}}}}{{{\rm d}T}}{\rm{ = }}\sqrt {\frac{{2{k_{\rm{b}}}}}{{{k_{\rm{u}}}{C_{{\rm{ox}}}}\left( {W/L} \right)}}} \left( {2 - \frac{1}{{\sqrt k }}} \right)\frac{{m + n}}{2}{T^{\frac{{m + n - 2}}{2}}} - {k_{{\rm{th}}}}.$$

(22)

The temperature coefficient of the reference V_ref1 can be approximately zero by setting the first order derivation of V_ref1 at zero at T₁ (−40 to 125 °C).

A small-signal power supply rejection ratio analysis is performed to illustrate the principle of the pre-regulated circuit deeply. We can obtain the following expressions by analyzing the relationship of voltage and current among nodes in the small-signal model.

$${V_{\rm{F}}} = \frac{{{R_2}}}{{{R_1} + {R_2}}}{V_{{\rm{reg}}}},$$

(23)

$${V_1} = A{V_{\rm{F}}},$$

(24)

$$\frac{{{V_{{\rm{dd}}}} - {V_{{\rm{reg}}}}}}{{{R_{{\rm{o}}1}}}} + {g_{{\rm{m}}1}}\left( {{V_{{\rm{dd}}}} - {V_1}} \right) = \frac{{{V_{{\rm{reg}}}}}}{{\left( {{R_1} + {R_2}} \right)//{R_{{\rm{BGR}}}}}},$$

(25)

where g_m1 is the transconductance of the transistor M1, R_O1 is the output impendence of the transistor M1, and R_BGR represents the effective impedance from the pre-regulated voltage V_reg to the ground node of the bandgap reference core circuit. A represents the open-loop gain of the op-amp. The power supply rejection ratio (PSRR) of the voltage V_reg can be derived from the relational expressions above:

$$\begin{split} {\rm {PSRR}}{_{V{\rm{reg}}}} &= 20\log \left( {\frac{{{V_{{\rm{reg}}}}}}{{{V_{{\rm{dd}}}}}}} \right)\\& = 20\log \left[ {\frac{{{g_{{\rm{m}}1}} + \frac{1}{{{R_{{\rm{O}}1}}}}}}{{{g_{{\rm{m}}1}}A\frac{{{R_2}}}{{{R_1} + {R_2}}} + \frac{1}{{{R_{{\rm{O}}1}}}} + \frac{1}{{\left( {{R_1} + {R_2}} \right)//{R_{{\rm{BGR}}}}}}}}} \right] \\& \approx 20\log \left[ {\frac{1}{A}\left( {1 + \frac{{{R_1}}}{{{R_2}}}} \right)} \right].\end{split}$$

(26)

From Eq. (26), the higher the open-loop gain A of the op-amp is, the lower the PSRR_Vreg is. The PSRR of the reference voltage V_ref can be expressed as follows:

$${\rm {PSRR}}{_{{\rm{Vref}}}} ={\rm {PSRR}}{_{{\rm{Vreg}}}} \times {\rm {PSRR}}{_{{\rm{Vref - Vreg}}}},$$

(27)

where PSRR_Vref-Vreg is the PSRR of V_ref to the pre-regulated voltage V_reg. It is concluded that the power supply voltage suppression performance of the bandgap reference voltage is improved by approximately A times and the supply noise is suppressed significantly by employing the proposed voltage pre-regulator circuit.

4. Circuit realization

The implementation of the proposed bandgap reference circuit is shown in Fig. 5. The voltage pre-regulator circuit generates a pre-regulated voltage to supply the BGR core circuit. Transistors N1–N4, P3, P4 and R1 constitute the biasing and reference voltage generator circuit. As a biasing circuit, it can provide a stable biasing current I_b, which does not change with the supply voltage. As a reference voltage generator circuit, it can provide the differential amplifier with a low temperature coefficient reference voltage (V_ref1). Transistors P5, P6, N5–N7 constitute a two-input differential amplifier, and the compensating capacitor (C_M) is used to ensure the stability of the feedback loop under a wide range of operating conditions and parameter variations. The pre-regulating technique greatly reduces the power supply voltage noise and fluctuations in the bandgap reference core circuit, and thus improves the supply voltage suppression performance and linear adjustment performance significantly.

As shown in Fig. 5, Transistors N11–N14, P17, P18 constitute the I_NL generating circuit. Transistors N11, N12, P17, P18 generate a constant current mirror. If the sizes of N11, N12 are equal and those of P17, P18, nodes V3 and V4 are forced to be at the same potential, thus the difference in gate-source voltage ΔV_GS between N13 and N14 is converted to nonlinear current I_NL by dividing resistor R7.

$${V_{{\rm{GS}}13}} = \sqrt {\frac{{2{I_{{\rm{NL}}}}}}{{{\mu _{\rm{n}}}{C_{{\rm{ox}}}}\left( {W/L} \right)}}} + {V_{{\rm{th}}}},$$

(28)

$${V_{{\rm{GS}}14}} = \sqrt {\frac{{2{I_{{\rm{NL}}}}}}{{{\mu _{\rm{n}}}{C_{{\rm{ox}}}}\left( {K \times W/L} \right)}}} + {V_{{\rm{th}}}},$$

(29)

where W and L are the channel width and channel length of N13 respectively, K is the ratio of the W/L of N14 and N13, μ_n represents n-type carrier mobility and it is negative related to temperature. Let I_NL = k₁T^m, μ_n = k₂T⁻ⁿ, k₁ and k₂ are parameters independent of temperature, m and n are temperature-independent numbers and values of them are about 1.5. Subtracting V_GS14 from V_GS13 gives the following expression:

$$\begin{split}\Delta {V_{{\rm{GS}}}} = {V_{{\rm{GS}}13}} - {V_{{\rm{GS}}14}} = \sqrt {\frac{{2{I_{{\rm{NL}}}}}}{{{\mu _{\rm{n}}}{C_{{\rm{ox}}}}\left( {W/L} \right)}}} \left( {1 - \sqrt {\frac{1}{K}} } \right)\\ = \sqrt {\frac{{2{k_1}}}{{{k_2}{C_{{\rm{ox}}}}\left( {W/L} \right)}}} \left( {1 - \sqrt {\frac{1}{K}} } \right){T^{\frac{{m + n}}{2}}}.\end{split}$$

(30)

The nonlinear temperature compensating current I_NL is created through the voltage ΔV_GS across the resistor R₇.

$${I_{{\rm{NL}}}} = \frac{{\Delta {V_{{\rm{GS}}}}}}{{{R_7}}}.$$

(31)

As can be seen in Fig. 5, the addition of CTAT current and PTAT current generated in the first-order current-mode BGR circuit is mirrored by P20 and the nonlinear corrected current I_NL is mirrored by P19. The sum of I_CTAT and I_PTAT and I_NL runs through R₇ to generate the output voltage V_ref. The output voltage V_ref can be written as:

$${V_{{\rm{ref}}}} = \left( {{I_{{\rm{CTAT}}}} + {I_{{\rm{PTAT}}}} + {I_{{\rm{NL}}}}} \right) {R_8} = \left( {\frac{{{V_{{\rm{BE}}}}}}{{{R_4}}} + \frac{{\Delta {V_{{\rm{BE}}}}}}{{{R_6}}} + \frac{{\Delta {V_{{\rm{GS}}}}}}{{{R_7}}}} \right){R_8}.$$

(32)

The V_ref can be expressed as a function of T by substituting Eqs. (4), (5), (6) and (30) into Eq. (32):

$$\begin{split}{V_{{\rm{ref}}}} =& - \frac{{{R_8}}}{{{R_4}}}\frac{{{V_{{\rm{g}}0}} - {V_{{\rm{BE}}0}} - \left( {{R_4}/{R_6}} \right){V_{{\rm{T}}0}}\ln \left( N \right) + \left( {\eta - 1} \right){V_{{\rm{T}}0}}}}{{{T_0}}} T\\& - \frac{{{R_8}}}{{{R_4}}}\frac{{\left( {\eta - 1} \right){V_{{\rm{T}}0}}}}{{{T_0}}}T\ln \left( {\frac{T}{{{T_0}}}} \right) + \frac{{{R_8}}}{{{R_7}}}{k_3}{T^{\frac{{m + n}}{2}}} + \frac{{{R_8}}}{{{R_4}}}{V_{{\rm{g}}0}},\end{split}$$

(33)

$${k_3} = \sqrt {\frac{{2{k_1}}}{{{k_2}{C_{{\rm{ox}}}}\left( {W/L} \right)}}} \left( {1 - \sqrt {\frac{1}{K}} } \right).$$

(34)

The first order and second order derivative of voltage V_ref can be expressed in the following form:

$$\begin{split}\frac{{{\rm d}{V_{{\rm{ref}}}}}}{{{\rm d}T}} = &- \frac{{{R_8}}}{{{R_4}}}\frac{{{V_{{\rm{g}}0}} - {V_{{\rm{BE}}0}} - \left( {{R_4}/{R_6}} \right){V_{{\rm{T}}0}}\ln \left( N \right) + \left( {\eta - 1} \right){V_{{\rm{T}}0}}}}{{{T_0}}}\\& - \frac{{{R_8}}}{{{R_4}}}\frac{{\left( {\eta - 1} \right){V_{{\rm{T}}0}}}}{{{T_0}}}\ln \left( {\frac{T}{{{T_0}}}} \right) + \frac{{{R_8}}}{{{R_7}}}{k_3}\frac{{m + n}}{2}{T^{\frac{{m + n - 2}}{2}}},\end{split}$$

(35)

$$\frac{{{{\rm d}^2}{V_{{\rm{ref}}}}}}{{{\rm d}{T^2}}} = - \frac{{{R_8}}}{{{R_4}}}\frac{{\left( {\eta - 1} \right){V_{{\rm{T}}0}}}}{{{T_0}}}\frac{1}{T} + \frac{{{R_8}}}{{{R_7}}}{k_3}\frac{{m + n}}{2}\frac{{m + n - 2}}{2}{T^{\frac{{m + n - 4}}{2}}}.$$

(36)

If the stationary point and inflection point of the temperature curve of the reference voltage V_ref are set as T₁ and T₂ respectively, we can obtain the following expression:

$${\left. {\frac{{{\rm d}{V_{{\rm{ref}}}}}}{{\rm d}T}} \right|_{T = {T_1}}} = 0,$$

(37)

$${\left. {\frac{{{{\rm d}^2}{V_{{\rm{ref}}}}}}{{{\rm d}{T^2}}}} \right|_{T = {T_2}}} = 0.$$

(38)

In order to attain a lower temperature coefficient over the temperature range from −40 to 125 °C, the values of T₁ and T₂ are supposed to be within the temperature range (−40 to 125 °C). The value of key resistors (R₄–R₈) can be inferred from the above relational expression and the current I_PTAT, I_CTAT and I_NL.

5. Results and discussion

The proposed BGR was designed in CSMC 0.5 μm 600 V BCD process and the layout is shown in Fig. 9. The robustness of the proposed BGR is verified by a corner simulation. Table 1 shows the simulated results of transistor corners. Fig. 6 shows the simulated and measured temperature characteristics. As shown in Table 1 and Fig. 6, the proposed BGR achieves TC of 0.144 ppm/°C in the best corner simulation (ff) and 0.159 ppm/°C in the worst corner simulation (ss). The measured temperature characteristic of the proposed BGR is 0.19 ppm/°C. Fig. 7 shows the simulated and measured PSRR performance. As shown in Table 1 and Fig. 7, the PSRR is slightly affected by transistor corners. The best case is −125.10 dB @ DC(tt) and −59.75 @ 100 kHz(ff). PSRR of −116.85 dB @ DC and −50.63 @ 100 kHz is achieved in the worst case (ss). The measured PSRR is −123 dB @ DC and −56 dB @ 100 kHz.

Fig. 8 shows reference voltage versus supply voltage at room temperature. It depicts that the circuit will deteriorate when the supply voltage is lower than 2.8 V. The proposed BGR has a line regulation performance of 0.017%/V in a range of different supply voltages (2.8–20 V).

Table 2 compares the performance of the BGR described in this paper to that of previously published BGRs. The BGR proposed in this paper shows the best performance in terms of TC and PSRR. However, the minimum power supply of the proposed BGR is higher than that in Refs. [11–17], which is mainly limited by the threshold of the MOS transistor of this process.

6. Conclusion

A high-order curvature-compensated CMOS bandgap reference (BGR) topology with low TC and high PSRR has been proposed. The presented circuit is designed and simulated in CSMC 0.5 μm 600 V BCD process. The experimental results show that the output reference voltage V_ref is 900.6 mV, and the TC is as low as 0.19 ppm/°C over a temperature range of 165 °C (−40 to 125 °C). The proposed BGR achieves PSRR of −123 dB @ DC and −56 dB @ 100 kHz. In addition, the circuit demonstrated very good line regulation performance for a broad range of supply voltages. The line regulation at room temperature is 0.017%/V in the supply range of 2.8–20 V.