J. Semicond. > 2021, Volume 42 > Issue 2 > 023101
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Mobility enhancement techniques for Ge and GeSn MOSFETs

Ran Cheng1, Zhuo Chen1, Sicong Yuan1, Mitsuru Takenaka3, Shinichi Takagi3, Genquan Han2 and Rui Zhang1,

+ Author Affiliations

 Corresponding author: Rui Zhang, ruizhang@zju.edu.cn

DOI: 10.1088/1674-4926/42/2/023101

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Abstract: The performance enhancement of conventional Si MOSFETs through device scaling is becoming increasingly difficult. The application of high mobility channel materials is one of the most promising solutions to overcome the bottleneck. The Ge and GeSn channels attract a lot of interest as the alternative channel materials, not only because of the high carrier mobility but also the superior compatibility with typical Si CMOS technology. In this paper, the recent progress of high mobility Ge and GeSn MOSFETs has been investigated, providing feasible approaches to improve the performance of Ge and GeSn devices for future CMOS technologies.

Key words: germanium, germanium-tin, MOSFET, mobility

In the past few decades, the device scaling of Si metal–oxide–semiconductor field-effect transistors (MOSFETs), following Moore’s Law, drives the fast development of complementary metal–oxide–semiconductor (CMOS) integrated circuits[1-3]. Recently, the performance enhancement of Si MOSFETs is increasingly difficult to achieve as the conventional device scaling is approaching its physical limit[4]. Higher channel mobility is effective to improve the MOSFETs performance, which has been well demonstrated by the application of strained-Si techniques[5, 6]. However, advanced MOSFET technology is still desired to further improve the performance of CMOS' devices. Alternative channel materials with mobility higher than Si have been attracting a lot of interest for the potential to improve the MOSFET performance. Among these high mobility materials, Ge and GeSn are promising candidates owing to their high mobility as well as the superior integrability on the Si platform[7-12].

It is essential to employ the high-k dielectrics (such as Al2O3, HfO2, etc.) for thinner equivalent oxide thickness (EOT), to satisfy the requirement of device scaling. Although the thin EOT high-k/Ge and high-k/GeSn MOSFETs have been demonstrated, the relatively low inversion carrier mobility severely limits the application of Ge and GeSn channels. This phenomenon attributes to the large interface state density (Dit) at the Ge and GeSn metal–oxide–semiconductor (MOS) interfaces, especially for the ultrathin Ge and GeSn gate stacks[13-18]. Thus the suppression of Dit in ultrathin EOT high-k/Ge and high-k/GeSn gate stacks would be one of the key issues to be resolved, in order to obtain high performance Ge and GeSn MOSFETs.

In this paper, the MOS interface passivation techniques from our previous work will be summarized for Ge and GeSn MOSFETs. Ge and GeSn MOSFETs with ultrathin EOT and superior channel mobility have been demonstrated, suggesting the great potential of Ge and GeSn MOSFETs as the alternative device structures in future advanced CMOS technologies.

2.1 EOT scaling and MOS interface passivation

Because of the large Dit at direct high-k/Ge interface, an interfacial layer (IL) is necessary to obtain the high mobility in Ge MOSFETs. It has been confirmed that the thermally oxidized GeO2/Ge interfaces are effective to passivate the Ge MOS interface, with a GeO2 thickness of ~20 nm[19-21]. However, the relatively low permittivity of GeO2 (5–6) requires the aggressive scaling down of the GeO2 thickness to achieve an ultrathin EOT high-k/GeO2/Ge gate stack. Unfortunately, it is difficult to fabricate a thin GeO2/Ge MOS interface with superior interface qualities, since the Dit in the IL significantly increases as the GeO2 thickness decreases[22, 23]. Therefore, the Dit reduction for thin GeO2/Ge MOS interfaces is one of the technical bottlenecks for the realization of high-performance Ge pMOSFETs.

To fabricate ultrathin Ge MOS interfaces with low Dit, a plasma post oxidation (PPO) method was proposed by using oxygen plasma exposure to oxidize the high-k/Ge interface (Fig. 1), yielding a high-k/GeOx/Ge gate stack[22, 24-25]. Here the high-k layer serves as a protecting layer to prevent damage to GeOx IL from the subsequent device fabrication process, and also as a sufficient oxygen barrier that suppresses the growth of unnecessarily thick GeOx IL. Fig. 2 shows the angel-resolved X-ray photoelectron spectroscopy (AR-XPS) spectra taken from an Al2O3 (1 nm)/Ge structure after PPO. The intensity of the Ge 3d peak corresponding to GeOx decreases more pronounced than that of the Al 2p peak corresponding to Al2O3, from which it is confirmed that the GeOx is formed underneath the Al2O3 layer after PPO.

Figure  1.  (Color online) The fabrication process of the high-k/GeOx/Ge gate stacks with PPO method.
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Figure  2.  (Color online) The AR-XPS spectra taken from an 1-nm-thick Al2O3/Ge structure with 650 W PPO for 10 s.
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The electrical properties of the PPO GeOx/Ge MOS interfaces were investigated using the Au/Al2O3/GeOx/Ge MOS capacitors. Fig. 3(a) shows the C–V curves of an Au/Al2O3 (1 nm)/GeOx (1.2 nm)/Ge MOS capacitor fabricated by PPO. The superior C–V characteristics are observed with an EOT of 1.06 nm. The Dit of this MOS capacitor was evaluated by the low temperature conductance method with the correction of surface potential fluctuation[26-29]. It is found that the reduction in Dit by one order of the magnitude is obtained after the PPO, as compared with that of the direct Al2O3/Ge MOS interface (Fig. 3(b)). The minimum Dit detected in this MOS capacitor is 5 × 1010 cm–2 eV–1. These results show a clear correlation between the high-k/Ge MOS interface quality with the existence of GeOx IL. The relationship between the GeOx/Ge MOS interface quality and the GeOx IL thickness is further studied. Here, the Al2O3 layer thickness (1 to 1.5 nm), oxygen plasma power (300 to 650 W), and plasma oxidation time (5 to 30 s) were varied to obtain different GeOx IL thicknesses. A thinner GeOx IL can be realized by lowering the plasma power, shortening the oxidation time, and increasing the thickness of the Al2O3 layer, which is attributable to the reduced diffusion of oxygen species through the Al2O3 layer. The GeOx ILs with the thickness ranging from 1.2 to 0.23 nm can be grown by changing the PPO conditions. Fig. 4 shows the Dit at the energy of Ei ‒ 0.2 eV for the Au/Al2O3/GeOx/Ge MOS capacitors as a function of the GeOx IL thickness, fabricated with various conditions. It is found that the Dit values of the Au/Al2O3/GeOx/Ge MOS capacitors fabricated with different conditions generally obey the universal relationship against the GeOx thickness. These results indicate that Dit at GeOx/Ge MOS interface is determined by neither the Al2O3 thickness nor the plasma conditions, but by the thickness of GeOx IL only. It is observed from this relationship that a significant degradation of Dit at the MOS interfaces starts around 0.5 nm. This phenomenon suggests that a GeOx IL with the thickness of one GeO2 unit cell (0.5–0.57 nm[30]), can sufficiently passivate a Ge MOS interface. This physical thickness of 0.5 nm corresponds roughly to a EOT of 0.35 nm under an assumption that the permittivity of GeOx is 5.5. As a result, the GeOx/Ge MOS interfaces with Dit lower than half of 1011 cm–2 eV–1 can be realized at the expense of increasing EOT by ~0.35 nm.

Figure  3.  (Color online) (a) The C–V characteristics of an Au/Al2O3 (1 nm)/GeOx (1.2 nm)/Ge MOS capacitor fabricated with the PPO method. (b) The Dit at the Al2O3/Ge MOS interfaces w/ and w/o PPO treatment.
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Figure  4.  (Color online) The Dit at Ei – 0.2 eV taken from PPO Al2O3/GeOx/Ge MOS interfaces fabricated with different Al2O3 capping thickness, plasma power and oxidation time.
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The GeOx IL shows a superior scalability to maintain the low Dit for Ge MOS interfaces, indicating a possibility to realize high quality Ge gate stacks with ultrathin EOT. The suppression of EOT contributed by a high-k layer is also important. The formation of high quality GeOx/Ge MOS interfaces has been studied for HfO2/Ge structures. The strong inter-mixing between HfO2 and Ge at high temperature induces the generation of MOS interface defects[31, 32]. Thus, the HfO2/Al2O3/Ge structure was used as the starting sample for PPO instead of the direct HfO2/Ge structure. Fig. 5(a) shows the C–V characteristic of an Au/Al2O3/GeOx/p-Ge MOS capacitor after PPO, as compared with that of the Au/HfO2 (2.2 nm)/p-Ge MOS capacitors w/ and w/o PPO. It is found that the capacitance increases for the gate stack using the HfO2 dielectrics, thanks to its large permittivity. However, the Au/HfO2 (2.2 nm)/p-Ge MOS capacitor shows a large stretch-out of the C–V curve even after PPO, suggesting that the PPO method is not effective to the HfO2/Ge gate stacks. This phenomenon is attributable to the significant degradation of Ge MOS interface quality and generation of Dit due to the HfGeOx formation induced by the HfO2–Ge inter-mixing. In contrast, the good C–V characteristics of the Au/HfO2/Al2O3/GeOx/p-Ge MOS capacitor indicate the sufficient passivation of the Ge MOS interface. The hysteresis of the C–V curves is ~150 mV for this MOS capacitor with a sweep scan from 1 to –1.5 V (data not shown), which is attributable to the slow traps in the HfO2 layer. A much smaller hysteresis was confirmed for the Al2O3/GeOx/Ge gate stack even with a much thicker EOT[22]. It is evaluated from a germanium based C–V simulator that the EOT of this MOS capacitor is 0.76 nm. The evaluated Dit values are plotted as a function of energy in the inset of Fig. 5(b). It is found that Dit of the Au/HfO2/Al2O3/GeOx/Ge MOS capacitor is suppressed by around one order of magnitude through PPO and that a minimum Dit value of 2 × 1011 cm–2 eV–1 is detected in this MOS capacitor. It is confirmed from the transmission electron microscopy (TEM) image that this gate stack is composed of HfO2/Al2O3/GeOx/Ge structure (Fig. 6). The ~0.55-nm-thick interfacial layer is observed between the 2.2-nm-thick HfO2 layer and the Ge substrate, corresponding to the 0.2-nm-thick Al2O3 diffusion control layer and the 0.35-nm-thick GeOx interfacial layer.

Figure  5.  (Color online) (a) The C–V curves of the Au/HfO2/p-Ge MOS capacitors w/ and w/o PPO, compared with that of Au/Al2O3/GeOx/p-Ge MOS capacitor. (b) The C–V curves of of the Au/HfO2/Al2O3/p-Ge MOS capacitor after PPO. The inset of it shows the energy distribution of Dit of this MOS capacitor.
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Figure  6.  The cross section TEM image of an HfO2 (2.2 nm)/Al2O3 (0.2 nm)/Ge structure after 15 s’ PPO using 500 W plasma.
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The impact of the PPO time on Dit and EOT of the Au/HfO2 (2.2 nm)/Al2O3 (0.2 nm)/GeOx/p-Ge MOS capacitors were examined. The Dit values at Ei ‒ 0.2 eV of these MOS capacitors are summarized in Fig. 7 as a function of EOT. The Dit taken from the PPO Al2O3/GeOx/Ge gate stacks is also shown for comparison. Due to the drastic increase of the gate leakage of the Al2O3/GeOx/Ge gate stacks with decreasing Al2O3 thickness, the thickness of GeOx IL has to be reduced to further scale down the EOT of Al2O3/GeOx/Ge gate stacks. As a result, the clear degradation of the MOS interface quality is observed as EOT approaches ~1 nm for Al2O3/GeOx/Ge gate stacks because of the insufficient GeOx IL thickness[24]. On the other hand, further EOT scaling is realized down to 0.7–0.8 nm for the HfO2/Al2O3/GeOx/Ge gate stacks because of the higher permittivity of HfO2. A rapid reduction of Dit at Ei ‒ 0.2 eV is observed from 5.3 to 3.9, 3.2, until 2.8 × 1011 cm–2 eV–1 with an increase in the PPO time from 5 to 10, 15, until 25 s for the HfO2 (2.2 nm)/Al2O3 (0.2 nm)/Ge gate stacks which have EOT of 0.72, 0.75, 0.76 and 0.82 nm, respectively. It is also confirmed from these results that the GeOx IL is necessary to maintain low Dit at the Ge MOS interface.

Figure  7.  (Color online) The Dit at the energy of Ei – 0.2 eV of the HfO2/Al2O3/GeOx/Ge and Al2O3/GeOx/Ge gate stacks, as a function of EOT.
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It is noted that in the HfO2/Al2O3/GeOx/Ge gate stacks, the thickness of the HfO2 layer was fixed at 2.2 nm to sufficiently suppress the gate leakage, while the EOT scaling capability of this gate stack structure is dominated by the GeOx IL thickness. Thus, it is still challenging to realize Ge gate stacks with thinner EOT but decently passivated MOS interface. Additionally, due to the directional nature of the oxygen plasma, it is difficult to realize an isotropic oxidation to 3D-structured Ge channels with the oxygen plasma. This phenomenon reduces the effectiveness of the PPO method to Ge FinFET or Ge gate-all-around devices, which are the most promising device structures for future Ge CMOS technology.

To solve these problems, an ozone post oxidation (OPO) was employed to form ultrathin Ge gate stacks with an isotropic oxidation (Fig. 8). After the ALD deposition of HfO2/Al2O3/Ge structures, the in-situ OPO was carried out at 300 °C in the 10% O3/O2 ambient with a pressure of ~100 Pa. The formation of the GeOx/Ge interface by OPO was examined by the cross-sectional TEM observation. As shown in Fig. 9, the gate stack with 60 s OPO shows a total physical thickness of 2.7 nm after 60 s OPO, indicating the growth of 0.4-nm-thick GeOx IL compared with the gate stack before OPO (2 nm HfO2/0.3 nm Al2O3). Here, the 0.3-nm-thick Al2O3 layer serves as a blocking layer to prevent the inter-mixing between HfO2 and GeOx during OPO. The partially crystallized HfO2 regions were observed in the HfO2 layer, which results in the increase of k value for HfO2[33]. The crystallization of HfO2 after OPO might be attributed to the slight Ge diffusion into the HfO2 film. Similar phenomena have also been reported in literature that the cubic phase HfO2 could be stabilized by Ge doping[34-37]. As a result, the EOT of the HfO2/Al2O3/GeOx/Ge gate stack is suppressed by the OPO treatment, and the ultrathin EOT of 0.6 nm has been obtained for the HfO2/Al2O3/GeOx/Ge gate stack with 60 s OPO. On the other hand, the EOT of the OPO HfO2/Al2O3/GeOx/Ge gate stack is thinner than the as-deposited HfO2/Al2O3/Ge gate stack (0.82 nm), although the total physical thickness of the gate stack increases after OPO due to the GeOx IL growth. This phenomenon is also observed for the HfO2/Al2O3/GeOx/Ge gate stacks with different Al2O3 layer thicknesses of 0.1 and 0.2 nm (Fig. 10). The relationship between Dit and EOT of the OPO HfO2/Al2O3/GeOx/Ge gate stacks is shown in Fig. 11, as compared with the PPO gate stacks. It is found that the Dit in the PPO HfO2/Al2O3/GeOx/Ge and Al2O3/GeOx/Ge gate stacks increase rapidly with the scaling down of the total EOT because it is mandatory to sacrifice the GeOx IL thickness during EOT scaling. The trade-off between EOT and Dit severely limits the scalability of these PPO gate stacks. In contrast, the lower Dit is obtained for the OPO HfO2/Al2O3/GeOx/Ge gate stacks with thinner EOT by increasing the OPO time, since the HfO2 crystallization compensates the EOT increase contributed by GeOx IL. These phenomena indicate that the OPO HfO2/Al2O3/GeOx/Ge gate stack features the superiority of both Dit suppression and EOT scalability, which is a promising gate stack technique for the future high performance Ge MOSFETs.

Figure  8.  (Color online) The schematic illusion of the ozone post oxidation process.
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Figure  9.  Cross section TEM of an HfO2 (2 nm)/Al2O3 (0.3 nm)/Ge structure after OPO for 60 s at 300 °C.
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Figure  10.  (Color online) The EOT of the OPO HfO2/Al2O3/GeOx/Ge gate stacks with different Al2O3 thicknesses and OPO times.
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Figure  11.  (Color online) The Dit at the energy of Ei – 0.2 eV in OPO HfO2/Al2O3/GeOx gate stacks, compared with the PPO gate stacks as a function of EOT.
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The effectiveness of the OPO method to the 3D-structured Ge channels was also examined using a series of Ge fins with the same fin height and different fin widths. The EOT on the sidewall and the EOT on the fin top are extracted for the PPO Al2O3/GeOx/Ge and the OPO HfO2/Al2O3/GeOx/Ge gate stacks. As shown in Fig. 12, the PPO Al2O3/GeOx/Ge gate stack has a thinner oxide thickness on the sidewall region than that at the bottom region, due to the insufficient formation of GeOx IL at the sidewall. In contrast, the OPO HfO2/Al2O3/GeOx/Ge gate stack shows almost the same oxide thickness for sidewall and bottom regions, meaning that the OPO exhibits an isotropic formation of GeOx IL. These results indicate the feasibility of OPO passivation for 3D-structured Ge channels.

Figure  12.  (Color online) The oxide thickness of the PPO and OPO gate stacks at side wall and top regions of a 3D structured Ge channel.
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2.2 Ultrathin EOT and high mobility Ge MOSFETs

The Ge MOSFETs have been demonstrated with the ultrathin EOT HfO2/Al2O3/GeOx gate stacks with OPO treatment. Gate first process was employed to fabricate the Ge MOSFETs with a structure shown in Fig. 13. The (100) n-Ge substrates with a resistivity of 1–10 Ω·cm were used. The SiO2 field oxide was deposited and the active areas were defined by etching off the SiO2. The HfO2/Al2O3/GeOx gate stacks were fabricated, and TiN gate electrodes were sputtered for the compatibility of process integration. The NiGe metal S/D structures were formed by Ni deposition and

Figure  13.  (Color online) The fabrication process of the Ge MOSFETs with OPO HfO2/Al2O3/GeOx gate stacks.
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NiGe metallization at 400 °C for 1 min. Finally, Ni contact pads were deposited on gate and S/D regions by thermal evaporation, for electrical characterization.

Figs. 14(a) and 14(b) show the Id–Vd and Id–Vg characteristics of an HfO2/Al2O3/GeOx/Ge pMOSFETs with 60 s OPO, respectively. The ON/OFF ratios of the NiGe S/D pMOSFETs are ~3.5 orders of magnitude. The S factor of 85 mV/decade could be obtained for the device, which corresponds to a Dit of 2.3 × 1012 cm–2 eV–1 and agrees well with the Dit measured by the conductance method. The normal operations of the Ge pMOSFETs with different OPO times are also observed (data not shown). The effective hole mobility of the Ge pMOSFETs were evaluated by the split C–V method. Fig. 15 shows the hole mobility in HfO2/Al2O3/GeOx/Ge pMOSFETs with different OPO times. The Ge pMOSFETs with OPO HfO2/Al2O3/GeOx/Ge gate stacks exhibit a much better improved hole mobility than that in HfO2/Al2O3/Ge pMOSFETs, attributing to the MOS interface passivation by OPO treatment. The peak hole mobility of 130, 332, 417 cm2/(V·s) were achieved with ultrathin EOT of 0.78, 0.72, and 0.58 nm, respectively. Conventionally, the mobility decreases with the scaling down of EOT for Ge MOSFETs, due to the degradation of MOS interfaces in the thinner gate stacks. However, it is interestingly noted that the hole mobility in the OPO HfO2/Al2O3/GeOx/Ge pMOSFETs increases with the decrease of EOT. This phenomenon is attributable to the different mechanisms of EOT scaling by OPO treatment and the conventional interface engineering techniques for Ge gate stacks. The EOT scaling was achieved by the permittivity enhancement of HfO2 after OPO treatment for the HfO2/Al2O3/GeOx/Ge gate stacks, rather than the decrease of GeOx interfacial layer thickness obtained from the conventional Ge gate stack treatments. Thus, the EOT scaling and mobility improvement are both realized for the OPO HfO2/Al2O3/GeOx/Ge MOSFETs.

Figure  14.  (Color online) The Id–Vd (a) and Id–Vg (b) characteristics of an (100)/<110> HfO2/Al2O3/GeOx/Ge pMOSFET fabricated by 60 s OPO.
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Figure  15.  (Color online) The hole mobility in HfO2/Al2O3/GeOx/Ge pMOSFET fabricated by OPO with different oxidation times, compared with that in the HfO2/Al2O3/Ge pMOSFET.
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3.1 MOS interface passivation

From the viewpoint of pursuing high mobility transistors, the alternative semiconductor materials are desired to further improve the CMOS performance. Although the Ge MOSFETs show promising properties to achieve an enhanced performance than the Si MOSFETs, the alternative channel materials are still mandatory for higher mobility MOSFETs. The GeSn channel MOSFETs are investigated as one of the possible solutions for future high mobility MOSFETs, especially for the high mobility pMOSFET applications. In contrast to the superior interface qualities of oxidation SiO2/Si and GeO2/Ge MOS interfaces, the oxidation GeSnOx/GeSn interface exhibits relatively high defect density[17]. Thus the passivation of GeSn MOS interface is one of the key issues that needs to be resolved in order to realize high-performance GeSn MOSFETs. Thanks to the different electrical potentials of the valence band of Si and GeSn, the Si IL passivation indicates a promising solution for GeSn MOS devices[38-40]. Due to the carrier confinement effect, the holes are repelled from the gate dielectric interface, resulting in a GeSn quantum well layer with a decreased inversion carrier scattering with reduced Coulomb and surface roughness scattering centers (Fig. 16).

Figure  16.  (Color online) The mechanism of suppressed carrier scattering in the Si passivated GeSn channel, compared with the direct oxide/GeSn channel.
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The Si passivation layers are grown on the surface of 6-nm-thick (100), (110) and (111) Ge0.92Sn0.08/Ge structures using MBE, with Si2H6 as the precursor. Fig. 17 shows the cross-section TEM image of a GeSn pMOSFET fabricated with the Si passivated GeSn substrate. Uniform layer thickness and sharp interface are observed for the Si/GeSn structure, indicating the successful formation of the GeSn quantum well channel. The pMOSFET devices with Si passivated Ge0.92Sn0.08 quantum well channels were fabricated with a gate first process. The TaN/HfO2 gate stacks were deposited on the Si/GeSn/Ge structures, followed by a post deposition annealing at 450 °C. After the gate patterning, the boron implantation and activation annealing were carried out to form the source/drain regions. The fabricated GeSn pMOSFETs exhibit normal operations as indicated by the Id–Vg and Id–Vd characteristics (Fig. 18). The peak mobility of 685, 745, and 845 cm2/(V·s) are obtained for (100), (110), and (111) GeSn pMOSFETs, respectively (Fig. 19). Additionally, the (100), (110), and (111) GeSn pMOSFETs exhibit the mobility of 445, 571, and 576 cm2/(V·s) at an Ns of 1013 cm–2, which is improved by 1.5 times as compared with those in the Ge pMOSFET control sample. The much higher hole mobility in the GeSn pMOSFETs as compared with that in Ge pMOSFETs are attributable to the high bulk mobility in GeSn and the carrier confinement effect by the Si passivation layer.

Figure  17.  The cross section TEM image of a GeSn MOS structure having the Si passivation.
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Figure  18.  (Color online) (a) Id–Vg and (b) Id–Vd characteristics of the (100) GeSn QW pMOSFET with Si passivation.
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Figure  19.  (Color online) The hole mobility in the Si passivated GeSn QW pMOSFETs with different channel orientations of (100), (110) and (111).
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3.2 Channel strain engineering

Beside of the MOS interface passivation, the strain engineering is also an effective performance booster to improve the mobility for GeSn pMOSFETs. It is found that the compressive strain induces the reduction of the hole effective mass and valence band edge lifting for GeSn channels, resulting in a higher hole mobility, which is similar to those in strained SiGe and Ge channels[5, 41-45]. Thus, it is essential to obtain the higher hole mobility in GeSn channels by enhancing the compressive strain. Since the GeSn channels are typically epitaxially grown on Si or Ge surfaces, the advantage of compressive strain for hole mobility improvement is expected to increase by improving the Sn composition in the GeSn channel. The 11-nm-thick GeSn channels were grown on (100) Ge surfaces with different Sn contents of 2.7%, 4.0%, and 7.5%, respectively. As a result, the biaxial compressive strain of 0.50%, 0.73%, and 1.35% were obtained in the GeSn channels. The in-situ Si2H6 treatment was employed to form the SiO2/Si passivation for GeSn channels, to suppress the inversion carrier scattering by MOS interface defects. It is confirmed from the cross-sectional TEM image that the total thickness of SiO2/Si passivation layers is ~1 nm for all samples, giving the same MOS interface passivation effect for GeSn channels with different Sn contents.

Fig. 20(a) shows the Id–Vd characteristics of the GeSn pMOSFETs with different Sn contents of 2.7%, 4.0% and 7.5%. The Id increase has been obtained for the GeSn pMOSFETs with the increased Sn content, which is attributable to the mobility enhancement. A similar phenomenon is also observed in the transconductance curves of these devices (Fig. 20(b)). It is also noted that the OFF-state current is larger for the GeSn pMOSFET with a higher Sn content, possibly caused by the reduced band gap due to the valent band edge lifting. The hole mobility in the GeSn pMOSFETs with different Sn contents are shown in Fig. 20(c). The improved hole mobility is confirmed for the GeSn pMOSFETs with an increase of Sn content, as theoretically predicted. The peak mobility of 340, 378, and 496 cm2/(V·s) are achieved for the GeSn pMOSFETs with Sn contents of 2.7%, 4.0%, and 7.5%, respectively.

Figure  20.  (Color online) The comparison of (a) Id–Vd curves, (b) Gm curves and (c) hole mobility of GeSn QW pMOSFETs with different Sn contents of 2.7%, 4.0% and 7.5%.
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The physical origin of the enhanced hole mobility in the GeSn channel with increased Sn content is investigated by performing the subband calculation using the 8 × 8 k∙p method, Schrödinger equation, and Poisson equation, with the material parameters taken from the Refs. [46, 47]. Fig. 21 shows the equi-energy contour plots of heavy hole (HH) bands for GeSn with different Sn contents of 2.7%, 4.0%, and 7.5%. It is found that the effective mass of hole decreases with the increase of Sn content, which is responsible for the increase of hole mobility in GeSn pMOSFETs.

Figure  21.  (Color online) The equienergy contours of heavy hole sub-band for GeSn pMOSFETs with different Sn contents of 2.7%, 4.0% and 7.5%, at a Ns of 5 × 1012 cm–2. The equienergy contour lines are for multiples of 20 meV.
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The Ge and GeSn channel MOSFETs have been examined to further improve the performance of CMOS technology. It is found that through the interface passivation with ultrathin GeOx layer grown by plasma post oxidation method, the mobility of Ge MOSFETs is sufficiently improved due to the Dit reduction. In addition, it is also confirmed that the Si passivation technique is an effective technique to enhance the mobility in the GeSn channel by suppressing the carrier scattering and reducing the hole effective mass especially for transistors with higher Sn content. These results indicate that the Ge and GeSn channels are one of the most promising solutions to realize future high-performance CMOS devices.

This work was supported, in part, by the Zhejiang Provincial Natural Science Foundation of China under Grant LR18F040001 and in part by the Fundamental Research Funds for the Central Universities.



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[12]
Lieten R R, Maeda T, Jevasuwan W, et al. Tensile-strained GeSn metal-oxide-semiconductor field-effect transistor devices on Si (111) using solid phase epitaxy. Appl Phys Exp, 2013, 6(10), 101301 doi: 10.7567/apex.6.101301
[13]
Xie R, Phung T H, He W, et al. High mobility high-k/Ge pMOSFETs with 1 nm EOT – New concept on interface engineering and interface characterization. IEDM Tech Dig, 2008, 393 doi: 10.1109/IEDM.2008.4796703
[14]
Mitard J, Shea C, DeJaeger B, et al. Impact of EOT scaling down to 0.85 nm on 70 nm Ge-pFETs technology with STI. VLSI Symp Tech Dig, 2009, 82
[15]
Kamata Y, Ikeda K, Kamimuta Y, et al. High-k/Ge p- & n-MISFETs with strontium germanide interlayer for EOT scalable CMIS application. VLSI Symp Tech Dig, 2009, 211 doi: 10.1109/VLSIT.2010.5556231
[16]
Gupta S, Vincent B, Yang B, et al. Towards high mobility GeSn channel nMOSFETs: Improved surface passivation using novel ozone oxidation method. IEDM Tech Dig, 2012, 16.2 doi: 10.1109/IEDM.2012.6479052
[17]
Liu L, Liang R R, Wang J, et al. Hole mobility enhancement of GeSn/Ge pMOSFETs with an interlayer formed by Sn-assisted oxynitridation. ECS Solid State Lett, 2014, 3(11), Q76 doi: 10.1149/2.0071411ssl
[18]
Haffner T, Mahjoub M A, Labau S, et al. Improvement of the electrical performance of Au/Ti/HfO2/Ge0.9Sn0.1 p-MOS capacitors by using interfacial layers. Appl Phys Lett, 2019, 115(17), 171601 doi: 10.1063/1.5121474
[19]
Nakakita Y, Nakane R, Sasada T, et al. Interface-controlled self-align source/drain Ge p-channel metal-oxide-semiconductor field-effect transistors fabricated using thermally oxidized GeO2 interfacial layers. Jpn J Appl Phys, 2011, 50(1), 010109 doi: 10.1109/IEDM.2008.4796838
[20]
Morii K, Iwasaki T, Nakane R, et al. High performance GeO2/Ge nMOSFETs with source/drain junctions formed by gas phase doping. IEEE Electron Device Lett, 2010, 31(10), 1092 doi: 10.1109/LED.2010.2061211
[21]
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[22]
Zhang R, Iwasaki T, Taoka N, et al. Al2O3/GeOx/Ge gate stacks with low interface trap density fabricated by electron cyclotron resonance plasma postoxidation. Appl Phys Lett, 2011, 98(11), 112902 doi: 10.1063/1.3564902
[23]
Zhang R, Iwasaki T, Taoka N, et al. Impact of GeOx interfacial layer thickness on Al2O3/Ge MOS interface properties. Microelectron Eng, 2011, 88(7), 1533 doi: 10.1016/j.mee.2011.03.130
[24]
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[25]
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Martens K, Jaeger B D, Bonzom R, et al. New interface state density extraction method applicable to peaked and high-density distributions for Ge MOSFET development. IEEE Electron Device Lett, 2006, 27(5), 405 doi: 10.1109/LED.2006.873767
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Van Elshocht S, Caymax M, Conard T, et al. Effect of hafnium germinate formation on the interface of HfO2/germanium metal oxide semiconductor devices. Appl Phys Lett, 2006, 88(14), 141904 doi: 10.1063/1.2192576
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[33]
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[35]
Tsoutsou D, Apostolopoulos G, Galata S, et al. Stabilization of a very high-k tetragonal ZrO2 phase by direct doping with germanium. Microelectron Eng, 2009, 86(7–9), 1626 doi: 10.1016/j.mee.2009.02.037
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[38]
Han G, Su S, Zhan C, Zhou Q, et al. High-mobility germanium-tin (GeSn) p-channel MOSFETs featuring metallic source/drain and sub-370 oC process modules. IEDM Tech Dig, 2011, 402 doi: 10.1109/IEDM.2011.6131569
[39]
Gupta S, Huang Y C, Kim Y, et al. Hole enhancement in compressively strained Ge0.93Sn0.07 pMOSFETs. IEEE Electron Device Lett, 2013, 34(7), 58 doi: 10.1109/LED.2013.2259573
[40]
Liu M, Han G, Liu Y, et al. Undoped Ge0.92Sn0.08 quantum well pMOSFETs on (001), (011) and (111) substrates with in situ Si2H6 passivation: High hole mobility and dependence of performance on orientation. VLSI Symp Tech Dig, 2014, 100 doi: 10.1109/VLSIT.2014.6894376
[41]
Mizuno T, Takagi S, Sugiyama N, et al. Electron and hole mobility enhancement in strained-Si MOSFET's on SiGe-on-insulator substrates fabricated by SIMOX technology. IEEE Electron Device Lett, 2000, 21(5), 230 doi: 10.1109/55.841305
[42]
Thompson S E, Armstrong M, Auth C, et al. A 90-nm logic technology featuring strained-silicon. IEEE Trans Electron Device, 2004, 51(11), 1790 doi: 10.1109/TED.2004.836648
[43]
Lee M L, Fitzgerald E A, Bulsara M T, et al. Strained Si, and Ge channels for high-mobility metal –oxide –semiconductor field-effect transistors. J Appl Phys, 2005, 97(1), 011101 doi: 10.1063/1.1819976
[44]
Nakaharai S, Tezuka T, Sugiyama N, et al. Characterization of 7-nm-thick strained Ge-on-insulator layer fabricated by Ge-condensation technique. Appl Phys Phys, 2003, 83(17), 3516 doi: 10.1063/1.1622442
[45]
Krishnamohan T, Krivokapic Z, Uchida K, et al. High-mobility ultrathin strained Ge MOSFETs on bulk and SOI with low band-to-band tunneling leakage: Experiments. IEEE Trans Electron Devices, 2006, 53(5), 990 doi: 10.1109/ted.2006.872362
[46]
Gupta S, Magyari-Kope B, Nishi Y, et al. Achieving direct band gap in germanium through integration of Sn alloying and external strain. J Appl Phys, 2014, 113(7), 073707 doi: 10.1063/1.4792649
[47]
Yang Y, Low K L, Wang W, et al. Germanium-tin n-channel tunneling field-effect transistor: Device physics and simulation study. J Appl Phys, 2013, 113(19), 194507 doi: 10.1063/1.4805051
Fig. 1.  (Color online) The fabrication process of the high-k/GeOx/Ge gate stacks with PPO method.

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Fig. 2.  (Color online) The AR-XPS spectra taken from an 1-nm-thick Al2O3/Ge structure with 650 W PPO for 10 s.

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Fig. 3.  (Color online) (a) The C–V characteristics of an Au/Al2O3 (1 nm)/GeOx (1.2 nm)/Ge MOS capacitor fabricated with the PPO method. (b) The Dit at the Al2O3/Ge MOS interfaces w/ and w/o PPO treatment.

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Fig. 4.  (Color online) The Dit at Ei – 0.2 eV taken from PPO Al2O3/GeOx/Ge MOS interfaces fabricated with different Al2O3 capping thickness, plasma power and oxidation time.

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Fig. 5.  (Color online) (a) The C–V curves of the Au/HfO2/p-Ge MOS capacitors w/ and w/o PPO, compared with that of Au/Al2O3/GeOx/p-Ge MOS capacitor. (b) The C–V curves of of the Au/HfO2/Al2O3/p-Ge MOS capacitor after PPO. The inset of it shows the energy distribution of Dit of this MOS capacitor.

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Fig. 6.  The cross section TEM image of an HfO2 (2.2 nm)/Al2O3 (0.2 nm)/Ge structure after 15 s’ PPO using 500 W plasma.

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Fig. 7.  (Color online) The Dit at the energy of Ei – 0.2 eV of the HfO2/Al2O3/GeOx/Ge and Al2O3/GeOx/Ge gate stacks, as a function of EOT.

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Fig. 8.  (Color online) The schematic illusion of the ozone post oxidation process.

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Fig. 9.  Cross section TEM of an HfO2 (2 nm)/Al2O3 (0.3 nm)/Ge structure after OPO for 60 s at 300 °C.

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Fig. 10.  (Color online) The EOT of the OPO HfO2/Al2O3/GeOx/Ge gate stacks with different Al2O3 thicknesses and OPO times.

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Fig. 11.  (Color online) The Dit at the energy of Ei – 0.2 eV in OPO HfO2/Al2O3/GeOx gate stacks, compared with the PPO gate stacks as a function of EOT.

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Fig. 12.  (Color online) The oxide thickness of the PPO and OPO gate stacks at side wall and top regions of a 3D structured Ge channel.

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Fig. 13.  (Color online) The fabrication process of the Ge MOSFETs with OPO HfO2/Al2O3/GeOx gate stacks.

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Fig. 14.  (Color online) The Id–Vd (a) and Id–Vg (b) characteristics of an (100)/<110> HfO2/Al2O3/GeOx/Ge pMOSFET fabricated by 60 s OPO.

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Fig. 15.  (Color online) The hole mobility in HfO2/Al2O3/GeOx/Ge pMOSFET fabricated by OPO with different oxidation times, compared with that in the HfO2/Al2O3/Ge pMOSFET.

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Fig. 16.  (Color online) The mechanism of suppressed carrier scattering in the Si passivated GeSn channel, compared with the direct oxide/GeSn channel.

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Fig. 17.  The cross section TEM image of a GeSn MOS structure having the Si passivation.

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Fig. 18.  (Color online) (a) Id–Vg and (b) Id–Vd characteristics of the (100) GeSn QW pMOSFET with Si passivation.

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Fig. 19.  (Color online) The hole mobility in the Si passivated GeSn QW pMOSFETs with different channel orientations of (100), (110) and (111).

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Fig. 20.  (Color online) The comparison of (a) Id–Vd curves, (b) Gm curves and (c) hole mobility of GeSn QW pMOSFETs with different Sn contents of 2.7%, 4.0% and 7.5%.

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Fig. 21.  (Color online) The equienergy contours of heavy hole sub-band for GeSn pMOSFETs with different Sn contents of 2.7%, 4.0% and 7.5%, at a Ns of 5 × 1012 cm–2. The equienergy contour lines are for multiples of 20 meV.

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Haffner T, Mahjoub M A, Labau S, et al. Improvement of the electrical performance of Au/Ti/HfO2/Ge0.9Sn0.1 p-MOS capacitors by using interfacial layers. Appl Phys Lett, 2019, 115(17), 171601 doi: 10.1063/1.5121474
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[22]
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[24]
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[31]
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[32]
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[33]
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[34]
Tsipas P, Volkos S N, Sotiropoulos A, et al. Germanium-induced stabilization of a very high-k zirconia phase in ZrO2/GeO2 gate stacks. Appl Phys Lett, 2008, 93(8), 082904 doi: 10.1063/1.2977555
[35]
Tsoutsou D, Apostolopoulos G, Galata S, et al. Stabilization of a very high-k tetragonal ZrO2 phase by direct doping with germanium. Microelectron Eng, 2009, 86(7–9), 1626 doi: 10.1016/j.mee.2009.02.037
[36]
Oshima Y, Shandalov M, Sun Y, et al. Hafnium oxide/germanium oxynitride gate stacks on germanium: Capacitance scaling and interface state density. Appl Phys Lett, 2009, 94(18), 183102 doi: 10.1063/1.3116624
[37]
Fu C H, Chang-Liao K S, Liu L J, et al. An ultralow EOT Ge MOS device with tetragonal HfO2 and high quality HfxGeyO interfacial layer. IEEE Trans Electron Devices, 2014, 61(8), 2662 doi: 10.1109/TED.2014.2329839
[38]
Han G, Su S, Zhan C, Zhou Q, et al. High-mobility germanium-tin (GeSn) p-channel MOSFETs featuring metallic source/drain and sub-370 oC process modules. IEDM Tech Dig, 2011, 402 doi: 10.1109/IEDM.2011.6131569
[39]
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[40]
Liu M, Han G, Liu Y, et al. Undoped Ge0.92Sn0.08 quantum well pMOSFETs on (001), (011) and (111) substrates with in situ Si2H6 passivation: High hole mobility and dependence of performance on orientation. VLSI Symp Tech Dig, 2014, 100 doi: 10.1109/VLSIT.2014.6894376
[41]
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[42]
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[44]
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[45]
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[46]
Gupta S, Magyari-Kope B, Nishi Y, et al. Achieving direct band gap in germanium through integration of Sn alloying and external strain. J Appl Phys, 2014, 113(7), 073707 doi: 10.1063/1.4792649
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Yang Y, Low K L, Wang W, et al. Germanium-tin n-channel tunneling field-effect transistor: Device physics and simulation study. J Appl Phys, 2013, 113(19), 194507 doi: 10.1063/1.4805051
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    Ran Cheng, Zhuo Chen, Sicong Yuan, Mitsuru Takenaka, Shinichi Takagi, Genquan Han, Rui Zhang. Mobility enhancement techniques for Ge and GeSn MOSFETs[J]. Journal of Semiconductors, 2021, 42(2): 023101. doi: 10.1088/1674-4926/42/2/023101
    R Cheng, Z Chen, S C Yuan, M Takenaka, S Takagi, G Q Han, R Zhang, Mobility enhancement techniques for Ge and GeSn MOSFETs[J]. J. Semicond., 2021, 42(2): 023101. doi: 10.1088/1674-4926/42/2/023101.
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    Received: 22 September 2020 Revised: 02 December 2020 Online: Accepted Manuscript: 16 December 2020Uncorrected proof: 17 December 2020Published: 08 February 2021

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      Article Navigation >  Journal of Semiconductors  > 2021  >  42(2): 023101
      Ran Cheng, Zhuo Chen, Sicong Yuan, Mitsuru Takenaka, Shinichi Takagi, Genquan Han, Rui Zhang. Mobility enhancement techniques for Ge and GeSn MOSFETs[J]. Journal of Semiconductors, 2021, 42(2): 023101. doi: 10.1088/1674-4926/42/2/023101 ****R Cheng, Z Chen, S C Yuan, M Takenaka, S Takagi, G Q Han, R Zhang, Mobility enhancement techniques for Ge and GeSn MOSFETs[J]. J. Semicond., 2021, 42(2): 023101. doi: 10.1088/1674-4926/42/2/023101.
      Citation:
      Ran Cheng, Zhuo Chen, Sicong Yuan, Mitsuru Takenaka, Shinichi Takagi, Genquan Han, Rui Zhang. Mobility enhancement techniques for Ge and GeSn MOSFETs[J]. Journal of Semiconductors, 2021, 42(2): 023101. doi: 10.1088/1674-4926/42/2/023101 ****
      R Cheng, Z Chen, S C Yuan, M Takenaka, S Takagi, G Q Han, R Zhang, Mobility enhancement techniques for Ge and GeSn MOSFETs[J]. J. Semicond., 2021, 42(2): 023101. doi: 10.1088/1674-4926/42/2/023101.
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      Mobility enhancement techniques for Ge and GeSn MOSFETs

      DOI: 10.1088/1674-4926/42/2/023101
      • 1.

        School of Micro-Nano Electronics, Zhejiang University, Hangzhou 310058, China

      • 2.

        State Key Discipline Laboratory of Wide Bandgap Semiconductor Technology, School of Microelectronics, Xidian University, Xi’an 710071, China

      • 3.

        School of Engineering, Tokyo University, Yayoi 2-11-16, Tokyo 113-8656, Japan

      More Information
      • Ran Cheng：received the B.Eng. and Ph.D degrees in Electrical Engineering from National University of Singapore, Singapore in 2009 and 2014, respectively. From late 2014, she joined School of Microelectronics, Zhejiang University. Her research interests include strain engineering, device modelling, fast and cyrogenic characterization for advanced transistors. She has authored and co-authored over 50 publications. She is currently an Associate Professor with Zhejiang University, China
      • Zhuo Chen：received the B.E. degree in materials science and engineering from Nanjing University of Aeronautics and Astronautics, Nanjing, China, in 2018. He is currently pursuing the M.E. degree with the School of Microelectronics, Zhejiang University, Hangzhou, China. He is currently engaged in the researches on Ge channel MOSFETs technology
      • Mitsuru Takenaka：was born in Kobe, Japan, in 1975. He received his B.E., M.E., and Ph.D. degrees in electronic engineering from the University of Tokyo, Japan, in 1998, 2000, and 2003, respectively. He is with the Department of Electrical Engineering and Information Systems, the University of Tokyo as a full professor. His research interests presently focus on the heterogeneous integration of III-V/Ge/2D materials on a Si platform for electronic-photonic integrated circuits
      • Shinichi Takagi：was born in Tokyo, Japan, on August 25, 1959. He received the B.S., M.S. and Ph.D. degrees in electronic engineering from the University of Tokyo, Tokyo, Japan, in 1982, 1984 and 1987, respectively. He joined the Toshiba Research and Development Center, Japan, in 1987. From 1993 to 1995, he was a Visiting Scholar at Stanford University. In October 2003, he moved to the University of Tokyo, where he is currently working as a professor in the department of Electrical Engineering and Information Systems. His recent interests include the science and the technologies of advanced CMOS devices
      • Genquan Han：received the B. Eng degree from Tsinghua University, Beijing, in 2003, and the Ph.D. degree from the Institute of Semiconductors, Chinese Academy of Sciences, Beijing, in 2008. He was a research fellow in National University of Singapore, from 2008 to 2013. In 2013, he joined College of Optoelectronic Engineering, Chongqing University. He is currently a Professor with the School of Microelectronics, Xidian University. His current research interests include high-mobility non-silicon MOSFETs, steep-slope field-effect transistors, novel non-volatile field-effect transistors, and Ga2O3 power devices
      • Rui Zhang：received the B.E. and M.E. degrees in materials science and engineering from Tsinghua University, Beijing, China, in 2006 and 2009, respectively, and the Ph.D. degree in electrical engineering from The University of Tokyo, Tokyo, Japan, in 2012. He is currently an Associate Professor with the Institute of Micro- and Nano-Electronics, Zhejiang University, Hangzhou, China. His current research interests include high mobility channel MOSFETs, novel computing devices and MOS structured sensor devices
      • Corresponding author: ruizhang@zju.edu.cn
      • Received Date: 2020-09-22
      • Revised Date: 2020-12-02
      • Published Date: 2021-02-10

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