Reliability evaluation on sense-switch p-channel flash

Side Song; Guozhu Liu; Hailiang Zhang; Lichao Chao; Jinghe Wei; Wei Zhao; Genshen Hong; Qi He

doi:10.1088/1674-4926/42/8/084101

J. Semicond. > 2021, Volume 42 > Issue 8 > 084101

ARTICLES

Reliability evaluation on sense-switch p-channel flash

Side Song¹, Guozhu Liu^{1, 2,}, Hailiang Zhang¹, Lichao Chao¹, Jinghe Wei¹, Wei Zhao¹, Genshen Hong¹ and Qi He¹

+ Author Affiliations

Corresponding author: Guozhu Liu, gzliucetc@163.com

DOI: 10.1088/1674-4926/42/8/084101

Abstract: In this paper, the reliability of sense-switch p-channel flash is evaluated extensively. The endurance result indicates that the p-channel flash could be programmed and erased for more than 10 000 cycles; the room temperature read stress shows negligible influence on the p-channel flash cell; high temperature data retention at 150 °C is extrapolated to be about 5 years and 53 years corresponding to 30% and 40% degradation in the drive current, respectively. Moreover, the electrical parameters of the p-channel flash at different operation temperature are found to be less affected. All the results above indicate that the sense-switch p-channel flash is suitable to be used as the configuration cell in flash-based FPGA.

Key words: reliability, endurance, data retention, sense-switch p-channel flash

References

[1]	Liu G Z. Characterization and modeling of a highly reliable ONO antifuse for high-performance FPGA and PROM. Int J Mater Sci Appl, 2016, 5, 169 doi: 10.11648/j.ijmsa.20160503.19
[2]	He T N, Zhang F C, Bhunia S, et al. Silicon carbide (SiC) nanoelectromechanical antifuse for ultralow-power one-time-programmable (OTP) FPGA interconnects. IEEE J Electron Devices Soc, 2015, 3, 323 doi: 10.1109/JEDS.2015.2421301
[3]	Rezzak N, Dsilva D, Wang J J, et al. SET and SEFI characterization of the 65 nm SmartFusion2 flash-based FPGA under heavy ion irradiation. 2015 IEEE Radiation Effects Data Workshop, 2015, 1
[4]	Zhang J, Zhou D M. An 8.5-ps two-stage vernier delay-line loop shrinking time-to-digital converter in 130-nm flash FPGA. IEEE Trans Instrum Meas, 2018, 67, 406 doi: 10.1109/TIM.2017.2769239
[5]	Li X L, Yu Q K, Sun Y, et al. The experimental study on SEU hardened effect of flash FPGA for space application. 2018 International Conference on Radiation Effects of Electronic Devices, 2018, 1
[6]	Rezgui S, Wang J J, Tung E C, et al. New methodologies for SET characterization and mitigation in flash-based FPGAs. IEEE Trans Nucl Sci, 2007, 54, 2512 doi: 10.1109/TNS.2007.910126
[7]	Ebrahimi M, Rao P M B, Seyyedi R, et al. Low-cost multiple bit upset correction in SRAM-based FPGA configuration frames. IEEE Trans Very Large Scale Integr (VLSI) Syst, 2016, 24, 932 doi: 10.1109/TVLSI.2015.2425653
[8]	Bernardeschi C, Cassano L, Domenici A. SRAM-based FPGA systems for safety-critical applications: A survey on design standards and proposed methodologies. J Comput Sci Technol, 2015, 30, 373 doi: 10.1007/s11390-015-1530-5
[9]	Wang J J, Rezzak N, Dsilva D, et al. A novel 65 nm radiation tolerant flash configuration cell used in RTG4 field programmable gate array. IEEE Trans Nucl Sci, 2015, 62, 3072 doi: 10.1109/TNS.2015.2495262
[10]	Rezzak N, Wang J J, Dsilva D, et al. TID and SEE characterization of microsemi's 4th generation radiation tolerant RTG4 flash-based FPGA. 2015 IEEE Radiation Effects Data Workshop, 2015, 1
[11]	Hsu C C H, Acovic A, Dori L, et al. A high speed, low power p-channel flash EEPROM using silicon rich oxide as tunneling dielectric. International Conference on Solid State Devices and Materials, 1992, 141
[12]	Liu G Z, Li B, Wei J H, et al. A radiation-hardened Sense-Switch pFLASH cell for FPGA. Microelectron Reliab, 2019, 103, 113514 doi: 10.1016/j.microrel.2019.113514
[13]	Liu G Z, Li B, Xiao Z Q, et al. The TID characteristics of a radiation hardened sense-switch pFLASH cell. IEEE Trans Device Mater Reliab, 2020, 20, 358 doi: 10.1109/TDMR.2020.2975825
[14]	Yamada S, Hiura Y, Yamane T, et al. Degradation mechanism of flash EEPROM programming after program/erase cycles. Proc IEEE Int Electron Devices Meet, 1993, 23
[15]	Schmid B A, Jia J Y, Wolfman J, et al. Cycling induced degradation of a 65 nm FPGA flash memory switch. IEEE International Integrated Reliability Workshop Final Report, 2010, 92
[16]	Chung S S, Kuo S N, Yih C M, et al. Performance and reliability evaluations of p-channel flash memories with different programming schemes. Int Electron Devices Meet IEDM Tech Dig, 1997, 295
[17]	Shiner R E, Caywood J M, Euzent B L. Data retention in EPROMS. 18th International Reliability Physics Symposium, 1980, 238
[18]	Mori S, Kaneko Y, Arai N, et al. Reliability study of thin inter-poly dielectrics for non-volatile memory application. 28th Annual Proceedings on Reliability Physics Symposium, 1990, 132

Fig. 1. (Color online) (a) The three-dimensional sense-switch p-channel flash diagram. (b) The basic working schematic.

DownLoad: Full-Size Img PowerPoint

Fig. 2. (Color online) (a) The threshold voltage and drive current as a function of the program and erase cycles. (b) Electron trapping in the tunnel oxide or spacer at the drain side when programmed.

DownLoad: Full-Size Img PowerPoint

Fig. 3. (Color online) (a) Current–time curve during read stress at room temperature. (b) I–V characteristic before and after read stress. I–V characteristic before and after high temperature storage (c) without cycling and (d) with 500 program and erase cycles before DRB. (e) Degradation of drive current versus time in bake. (f) I–V characteristic of the erased state device under high temperature storage.

DownLoad: Full-Size Img PowerPoint

Fig. 4. (Color online) (a) The output characteristics of the programmed switch. (b) The programmed and erased state of the switch under different temperatures. (c) The threshold voltage and drive current with different temperature cycling.

DownLoad: Full-Size Img PowerPoint

[1]	Liu G Z. Characterization and modeling of a highly reliable ONO antifuse for high-performance FPGA and PROM. Int J Mater Sci Appl, 2016, 5, 169 doi: 10.11648/j.ijmsa.20160503.19
[2]	He T N, Zhang F C, Bhunia S, et al. Silicon carbide (SiC) nanoelectromechanical antifuse for ultralow-power one-time-programmable (OTP) FPGA interconnects. IEEE J Electron Devices Soc, 2015, 3, 323 doi: 10.1109/JEDS.2015.2421301
[3]	Rezzak N, Dsilva D, Wang J J, et al. SET and SEFI characterization of the 65 nm SmartFusion2 flash-based FPGA under heavy ion irradiation. 2015 IEEE Radiation Effects Data Workshop, 2015, 1
[4]	Zhang J, Zhou D M. An 8.5-ps two-stage vernier delay-line loop shrinking time-to-digital converter in 130-nm flash FPGA. IEEE Trans Instrum Meas, 2018, 67, 406 doi: 10.1109/TIM.2017.2769239
[5]	Li X L, Yu Q K, Sun Y, et al. The experimental study on SEU hardened effect of flash FPGA for space application. 2018 International Conference on Radiation Effects of Electronic Devices, 2018, 1
[6]	Rezgui S, Wang J J, Tung E C, et al. New methodologies for SET characterization and mitigation in flash-based FPGAs. IEEE Trans Nucl Sci, 2007, 54, 2512 doi: 10.1109/TNS.2007.910126
[7]	Ebrahimi M, Rao P M B, Seyyedi R, et al. Low-cost multiple bit upset correction in SRAM-based FPGA configuration frames. IEEE Trans Very Large Scale Integr (VLSI) Syst, 2016, 24, 932 doi: 10.1109/TVLSI.2015.2425653
[8]	Bernardeschi C, Cassano L, Domenici A. SRAM-based FPGA systems for safety-critical applications: A survey on design standards and proposed methodologies. J Comput Sci Technol, 2015, 30, 373 doi: 10.1007/s11390-015-1530-5
[9]	Wang J J, Rezzak N, Dsilva D, et al. A novel 65 nm radiation tolerant flash configuration cell used in RTG4 field programmable gate array. IEEE Trans Nucl Sci, 2015, 62, 3072 doi: 10.1109/TNS.2015.2495262
[10]	Rezzak N, Wang J J, Dsilva D, et al. TID and SEE characterization of microsemi's 4th generation radiation tolerant RTG4 flash-based FPGA. 2015 IEEE Radiation Effects Data Workshop, 2015, 1
[11]	Hsu C C H, Acovic A, Dori L, et al. A high speed, low power p-channel flash EEPROM using silicon rich oxide as tunneling dielectric. International Conference on Solid State Devices and Materials, 1992, 141
[12]	Liu G Z, Li B, Wei J H, et al. A radiation-hardened Sense-Switch pFLASH cell for FPGA. Microelectron Reliab, 2019, 103, 113514 doi: 10.1016/j.microrel.2019.113514
[13]	Liu G Z, Li B, Xiao Z Q, et al. The TID characteristics of a radiation hardened sense-switch pFLASH cell. IEEE Trans Device Mater Reliab, 2020, 20, 358 doi: 10.1109/TDMR.2020.2975825
[14]	Yamada S, Hiura Y, Yamane T, et al. Degradation mechanism of flash EEPROM programming after program/erase cycles. Proc IEEE Int Electron Devices Meet, 1993, 23
[15]	Schmid B A, Jia J Y, Wolfman J, et al. Cycling induced degradation of a 65 nm FPGA flash memory switch. IEEE International Integrated Reliability Workshop Final Report, 2010, 92
[16]	Chung S S, Kuo S N, Yih C M, et al. Performance and reliability evaluations of p-channel flash memories with different programming schemes. Int Electron Devices Meet IEDM Tech Dig, 1997, 295
[17]	Shiner R E, Caywood J M, Euzent B L. Data retention in EPROMS. 18th International Reliability Physics Symposium, 1980, 238
[18]	Mori S, Kaneko Y, Arai N, et al. Reliability study of thin inter-poly dielectrics for non-volatile memory application. 28th Annual Proceedings on Reliability Physics Symposium, 1990, 132

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Received: 03 February 2021 Revised: 02 March 2021 Online: Accepted Manuscript: 26 April 2021Uncorrected proof: 10 May 2021Published: 01 August 2021

Article Navigation > Journal of Semiconductors > 2021 > 42(8): 084101

Side Song, Guozhu Liu, Hailiang Zhang, Lichao Chao, Jinghe Wei, Wei Zhao, Genshen Hong, Qi He. Reliability evaluation on sense-switch p-channel flash[J]. Journal of Semiconductors, 2021, 42(8): 084101. doi: 10.1088/1674-4926/42/8/084101 ****S D Song, G Z Liu, H L Zhang, L C Chao, J H Wei, W Zhao, G S Hong, Q He, Reliability evaluation on sense-switch p-channel flash[J]. J. Semicond., 2021, 42(8): 084101. doi: 10.1088/1674-4926/42/8/084101.

Citation:

Side Song, Guozhu Liu, Hailiang Zhang, Lichao Chao, Jinghe Wei, Wei Zhao, Genshen Hong, Qi He. Reliability evaluation on sense-switch p-channel flash[J]. Journal of Semiconductors, 2021, 42(8): 084101. doi: 10.1088/1674-4926/42/8/084101 ****

S D Song, G Z Liu, H L Zhang, L C Chao, J H Wei, W Zhao, G S Hong, Q He, Reliability evaluation on sense-switch p-channel flash[J]. J. Semicond., 2021, 42(8): 084101. doi: 10.1088/1674-4926/42/8/084101.

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Reliability evaluation on sense-switch p-channel flash

DOI: 10.1088/1674-4926/42/8/084101

1.
The 58th Institution of Electronic Science and Technology Group Corporation of China, Wuxi 214035, China
2.
School of Electronic Science and Engineering, Southeast University, Nanjing 210096, China

More Information

Side Song：received the M.S. degree in Material Physics and Chemistry from the Shandong University of China. He is currently a senior engineer in the 58th Institution of Electronic Science and Technology Group Corporation of China. His research interests include semiconductor device and process integration
Guozhu Liu：received the M.S. degree in Applied Chemistry from the University of Electronic Science and Technology of China in 2009. He is currently pursuing the Ph.D. degree in Electronics and Information in Southeast University. He is currently a senior engineer in the 58th Institution of Electronic Science and Technology Group Corporation of China. His research interests include semiconductor devices and process integration
Corresponding author: gzliucetc@163.com
Received Date: 2021-02-03
Revised Date: 2021-03-02
Published Date: 2021-08-10

Abstract

Abstract

In this paper, the reliability of sense-switch p-channel flash is evaluated extensively. The endurance result indicates that the p-channel flash could be programmed and erased for more than 10 000 cycles; the room temperature read stress shows negligible influence on the p-channel flash cell; high temperature data retention at 150 °C is extrapolated to be about 5 years and 53 years corresponding to 30% and 40% degradation in the drive current, respectively. Moreover, the electrical parameters of the p-channel flash at different operation temperature are found to be less affected. All the results above indicate that the sense-switch p-channel flash is suitable to be used as the configuration cell in flash-based FPGA.
- reliability,
- endurance,
- data retention,
- sense-switch p-channel flash

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References(18)

References

[1]	Liu G Z. Characterization and modeling of a highly reliable ONO antifuse for high-performance FPGA and PROM. Int J Mater Sci Appl, 2016, 5, 169 doi: 10.11648/j.ijmsa.20160503.19
[2]	He T N, Zhang F C, Bhunia S, et al. Silicon carbide (SiC) nanoelectromechanical antifuse for ultralow-power one-time-programmable (OTP) FPGA interconnects. IEEE J Electron Devices Soc, 2015, 3, 323 doi: 10.1109/JEDS.2015.2421301
[3]	Rezzak N, Dsilva D, Wang J J, et al. SET and SEFI characterization of the 65 nm SmartFusion2 flash-based FPGA under heavy ion irradiation. 2015 IEEE Radiation Effects Data Workshop, 2015, 1
[4]	Zhang J, Zhou D M. An 8.5-ps two-stage vernier delay-line loop shrinking time-to-digital converter in 130-nm flash FPGA. IEEE Trans Instrum Meas, 2018, 67, 406 doi: 10.1109/TIM.2017.2769239
[5]	Li X L, Yu Q K, Sun Y, et al. The experimental study on SEU hardened effect of flash FPGA for space application. 2018 International Conference on Radiation Effects of Electronic Devices, 2018, 1
[6]	Rezgui S, Wang J J, Tung E C, et al. New methodologies for SET characterization and mitigation in flash-based FPGAs. IEEE Trans Nucl Sci, 2007, 54, 2512 doi: 10.1109/TNS.2007.910126
[7]	Ebrahimi M, Rao P M B, Seyyedi R, et al. Low-cost multiple bit upset correction in SRAM-based FPGA configuration frames. IEEE Trans Very Large Scale Integr (VLSI) Syst, 2016, 24, 932 doi: 10.1109/TVLSI.2015.2425653
[8]	Bernardeschi C, Cassano L, Domenici A. SRAM-based FPGA systems for safety-critical applications: A survey on design standards and proposed methodologies. J Comput Sci Technol, 2015, 30, 373 doi: 10.1007/s11390-015-1530-5
[9]	Wang J J, Rezzak N, Dsilva D, et al. A novel 65 nm radiation tolerant flash configuration cell used in RTG4 field programmable gate array. IEEE Trans Nucl Sci, 2015, 62, 3072 doi: 10.1109/TNS.2015.2495262
[10]	Rezzak N, Wang J J, Dsilva D, et al. TID and SEE characterization of microsemi's 4th generation radiation tolerant RTG4 flash-based FPGA. 2015 IEEE Radiation Effects Data Workshop, 2015, 1
[11]	Hsu C C H, Acovic A, Dori L, et al. A high speed, low power p-channel flash EEPROM using silicon rich oxide as tunneling dielectric. International Conference on Solid State Devices and Materials, 1992, 141
[12]	Liu G Z, Li B, Wei J H, et al. A radiation-hardened Sense-Switch pFLASH cell for FPGA. Microelectron Reliab, 2019, 103, 113514 doi: 10.1016/j.microrel.2019.113514
[13]	Liu G Z, Li B, Xiao Z Q, et al. The TID characteristics of a radiation hardened sense-switch pFLASH cell. IEEE Trans Device Mater Reliab, 2020, 20, 358 doi: 10.1109/TDMR.2020.2975825
[14]	Yamada S, Hiura Y, Yamane T, et al. Degradation mechanism of flash EEPROM programming after program/erase cycles. Proc IEEE Int Electron Devices Meet, 1993, 23
[15]	Schmid B A, Jia J Y, Wolfman J, et al. Cycling induced degradation of a 65 nm FPGA flash memory switch. IEEE International Integrated Reliability Workshop Final Report, 2010, 92
[16]	Chung S S, Kuo S N, Yih C M, et al. Performance and reliability evaluations of p-channel flash memories with different programming schemes. Int Electron Devices Meet IEDM Tech Dig, 1997, 295
[17]	Shiner R E, Caywood J M, Euzent B L. Data retention in EPROMS. 18th International Reliability Physics Symposium, 1980, 238
[18]	Mori S, Kaneko Y, Arai N, et al. Reliability study of thin inter-poly dielectrics for non-volatile memory application. 28th Annual Proceedings on Reliability Physics Symposium, 1990, 132

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