J. Semicond. > 2022, Volume 43 > Issue 10 > 104102
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ARTICLES

A deep trench super-junction LDMOS with double charge compensation layer

Lijuan Wu, Shaolian Su, Xing Chen, Jinsheng Zeng and Haifeng Wu

+ Author Affiliations

 Corresponding author: Lijuan Wu, 305719669@qq.com

DOI: 10.1088/1674-4926/43/10/104102

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Abstract: A deep trench super-junction LDMOS with double charge compensation layer (DC DT SJ LDMOS) is proposed in this paper. Due to the capacitance effect of the deep trench which is known as silicon–insulator–silicon (SIS) capacitance, the charge balance in the super-junction region of the conventional deep trench SJ LDMOS (Con. DT SJ LDMOS) device will be broken, resulting in breakdown voltage (BV) of the device drops. DC DT SJ LDMOS solves the SIS capacitance effect by adding a vertical variable doped charge compensation layer and a triangular charge compensation layer inside the Con. DT SJ LDMOS device. Therefore, the drift region reaches an ideal charge balance state again. The electric field is optimized by double charge compensation and gate field plate so that the breakdown voltage of the proposed device is improved sharply, meanwhile the enlarged on-current region reduces its specific on-resistance. The simulation results show that compared with the Con. DT SJ LDMOS, the BV of the DC DT SJ LDMOS has been increased from 549.5 to 705.5 V, and the Ron,sp decreased to 23.7 mΩ·cm2.

Key words: double charge compensation layer, super-junction, deep trench, SIS capacitance

Super-junction (SJ) technology has become a milestone in the history of power devices because it has broken the "silicon limit"[1, 2]. However, because the traditional LDMOS relies on a large cell pitch to sustain surface voltage, the benefit brought by SJ is limited. This problem is solved by the deep-trench (DT) technique, in which a DT filled with dielectric is utilized to sustain most of the surface voltage[3-8]. However, in the Con. DT SJ LDMOS, due to the existence of the SIS capacitance, the charge balance in the SJ region is broken, which causes damage of the performance of the device[9-12].

This paper develops a solution by adding vertical variable doping layer at the source end of the SiO2 trench and an inverted triangular charge compensation layer at the drain end to compensate the unbalanced charge in the SJ region caused by the SIS capacitance effect on both sides of the SiO2 dielectric trench, and optimize the surface electric field of the device. The SJ region on the source side of the DC DT SJ LDMOS is a P–N–P type super junction structure. The introduction of this P–N–P SJ structure adds a new voltage-resistant junction compared to the Con. P–N SJ structure to modulate the internal electric field and produces a new electric field peak which raises the internal electric field of the device.

The structure of the DC DT SJ LDMOS is shown as Fig. 1(a). tsj, tdrift, and tsub represent the thickness of the SJ, the thickness of the bottom drift region and the thickness of the substrate respectively, Wsj represents the width of the super junction on both sides of the SiO2 dielectric trench, and the width of the compensation layer is equal to the width of the SJ region. Wtrench is the width of the SiO2 dielectric trench. Ndrift and Nsub are the doping concentration of the drift region at the bottom of the SiO2 dielectric trench and the doping concentration of the substrate, respectively. The doping concentration of the P–N–P type SJ region under the source is the same, NA1 = ND1 = Nsj. The doping concentration of the triangle-like SJ region under the drain level is the same, NA2 = ND2 = Nsj2. The concentration of the triangular charge compensation layer on the left side of the SiO2 dielectric trench is NTB. The charge compensation layer on the right side of the SiO2 dielectric trench is vertical variable-doped, and the doping concentration gradually decreases from the top to the bottom, which is represented by NVB.

Fig. 1.  (Color online) The structure of (a) DC DT SJ LDMOS and (b) Con. DT SJ LDMOS.
DownLoad: Full-Size Img PowerPoint

As can seen from the Fig. 1(a), the DC DT SJ LDMOS device structure has a triangular charge compensation layer on the left side of the SiO2 dielectric trench. The addition of the triangular charge compensation layer makes the conventional P-pillar and N-pillar SJ structure with equal width and equal concentration become a triangular-like SJ structure. The inverted triangle form of the charge compensation layer fully compensates the charge accumulated by the SIS parallel plate capacitance generated on both sides of the SiO2 dielectric trench. The right-hand side of the SiO2 dielectric trench adopts the P-type charge compensation layer in the form of vertical variable doping. The P-type gradient compensation layer can also fully compensate the charge generated by the SIS capacitor, and the SJ region returns to the charge balance state. The SJ region at the source side of the SiO2 dielectric trench is a P–N–P type SJ structure. The addition of a new voltage-resistant junction improves the BV of the device in both horizontal and vertical directions. The structure of the Con. DT SJ LDMOS is shown in Fig. 1(b).

The main parameters of the device structure of DC DT SJ LDMOS are shown in Table 1.

Table 1.  Key parameters used in simulation.
ParameterSymbolDC DT SJ LDMOSCon. DT SJ LDMOSUnit
Width of SiO2 trenchWtrench1010μm
Width of PN pillarWsj22μm
Thickness of PN pillartsj1717μm
Thickness of drift regiontdrift22μm
Thickness of substratetsub3838μm
Doping concentration of N/P pillar at sourceND1/NA1(Nsj)OptimizedOptimizedcm–3
Doping concentration of triangular-like SJ N/P pillar at drainND2/NA2(Nsj2)OptimizedOptimizedcm–3
Doping concentration of inverted triangular charge compensation layerNTBOptimized–cm–3
Vertical variable doping concentrationNVBOptimized–cm–3
Doping concentration of N drift regionNdriftOptimizedOptimizedcm–3
DownLoad: CSV  | Show Table

Fig. 2 shows the charge compensation principle of the DC DT SJ LDMOS. The vertical variable-doped P pillar at the source side and the inverted triangular N pillar at the drain side are used to compensate for the vertically distributed charges accumulated on both sides of the trench SiO2 capacitor. The triangular-like SJ structure at the source side and the PNP structure at the drain side can deplete each other and maintain charge balance, so that the device reaches the charge balance.

Fig. 2.  (Color online) Structure and composition of the DC DT SJ LDMOS.
DownLoad: Full-Size Img PowerPoint

Compared with the structure of the Con. DT SJ LDMOS device, the problem of charge imbalance due to SIS capacitance can be solved. The P–N–P type SJ structure at the source can modulate the internal electric field of the device.

The BV of DC DT SJ LDMOS has increased by 28.9% to 705.5 V. In the on-state, the current path is widen at the drain, and the doping concentration of triangular-like SJ region at the drain and P–N–P structure source is higher than that of the Con. DT SJ LDMOS so the Ron,sp can be reduced significantly.

The vertical variable-doped P-type charge compensation layer provides more uniform and sufficient charge compensation for the charge imbalance in the SJ region caused by the SIS capacitors on both sides of the SiO2 dielectric trench. The change gradient of the vertical concentration of the P-type charge compensation layer is optimized by simulation.

The doping concentration of the P-type charge compensation layer on the right-hand side of the SiO2 dielectric trench changes linearly. The position of the charge compensation layer is 3 to 20 μm in the y direction, and the thickness is 17 μm. The doping concentration gradually decreased from 2 × 1015 to 1 × 1015 cm−3. The concentration change gradient formula is:

NVB=20−y17NVB,max +NVB,min.
 (1)

This section discusses the effects of ND1, NA1, ND2, NA2, Ndrift, NTB and NVB on the BV, Ron,sp and FOM of the DC DT SJ LDMOS device. The above structure parameters were optimized by simulation.

Fig. 3 depicts the variation of the BV of the Con. DT SJ LDMOS and DC DT SJ LDMOS device with the Nsj at the source. It can be seen from the figure that the optimal value of the BV of the Con. DT SJ LDMOS is just 549.5 when the Nsj is 5 × 1015 cm−3 while the BV of the DC DT SJ LDMOS reaches a maximum of 705.5 V when the Nsj is 1.2 × 1016 cm−3. For the DC DT SJ LDMOS, when the Nsj ≤ 1.2 × 1016 cm−3, the BV increases with the Nsj. This happens because the electron-hole pairs in the device were not fully depleted and the space charge region formed by the PN junction will form an electric field spike, leading to premature breakdown of the device. After the Nsj exceeds the optimal value, the BV decreases with the increase of Nsj, because the excess electrons or holes cannot be completely depleted, the BV begins to drop again.

Fig. 3.  (Color online) The influence of Nsj at source on BV of Con. DT SJ LDMOS and DC DT SJ LDMOS.
DownLoad: Full-Size Img PowerPoint

Fig. 4 shows the BV and FOM of the DC DT SJ LDMOS device with the change of the triangle-like SJ doping concentration Nsj2 at the drain side. The two curves of the device show a trend of first rising and then falling. When the concentration of Nsj2 is 7 × 1015 cm−3, the BV and FOM reach the maximum. The reason of this trend is similar to Fig. 3, which is related to the depletion of electron-hole pairs.

Fig. 4.  (Color online) The influence of Nsj2 at the drain on BV of DC DT SJ LDMOS.
DownLoad: Full-Size Img PowerPoint

Fig. 5 shows the influence of NTB at the drain side on BV and FOM for the DC DT SJ LDMOS. The N-type region in the triangular SJ will not only deplete part of the charge through the SIS capacitance effect but also deplete with the P-type region. To achieve charge balance, a triangular charge compensation layer under the drain is added to compensate for holes that are not depleted in the P-type SJ region due to the SIS capacitance effect. The optimization of the doping concentration NTB in the triangular charge compensation layer can better solve the charge imbalance issue caused by the SIS capacitance effect. The compensation layer is an inverted triangle, which is uniformly doped, and the amount of compensation charge gradually decreases from the top to the bottom. Since the SJ region is in charge unbalanced state, which is affected by the SIS capacitance and will result in a decrease in BV.

Fig. 5.  (Color online) The influence of NTB at the drain on BV of DC DT SJ LDMOS.
DownLoad: Full-Size Img PowerPoint

It is very sensitive for BV that the changes in concentration of the charge compensation layer may cause a decay in its value.

It can be seen from Fig. 5 that when the triangular charge compensation layer NTB = 5 × 1015 cm−3, the BV and FOM reached the maximum. Both curves show a trend of increasing first and then decreasing, when the doping concentration increases from 1 × 1015 to 5 × 1015 cm−3.

Fig. 6 shows how the change of vertical variable charge compensation layer doping concentration NVB influences BV and FOM. The doping concentration of the vertical variable doped charge compensation layer decreases with the increase of Y, and the doping concentration change is shown as Eq. (1). As shown in Fig. 6, when NVB,min = 1 × 1015 cm−3 and NVB,max = 1 × 1015 cm−3, the BV reaches the maximum. When the BV reaches the optimal value, the maximum concentration of the linear variable doping is 2 × 1015 cm−3. When the concentration of the vertical variable doping region is optimized to the optimum, the problem caused by the SIS capacitance effect in the SJ region is solved, and the SJ region returns to the charge balance state. The BV of DC DT SJ LDMOS device rises. The Ron,sp is not affected by doping concentration. This happens because the current does not flow through the vertical variable doping P pillar. Consequently, when the BV achieves the optimal value, the FOM also achieves the optimal value.

Fig. 6.  (Color online) The influence of NVB on BV of DC DT SJ LDMOS. (a) Influence of NVB, max on BV of DC DT SJ LDMOS. (b) Influence of NVB,min on BV of DC DT SJ LDMOS.
DownLoad: Full-Size Img PowerPoint

Fig. 7 shows the influence of Ndrift on the BV and FOM of Con. DT SJ LDMOS and DC DT SJ LDMOS. From the figure it can be seen when the BV reaches the optimal value, the Ndrift are 5 × 1015 and 7 × 1015 cm−3. The Ndrift of DC DT SJ LDMOS is higher than that of Con. DT SJ LDMOS. The N-type drift region at the bottom of the trench is mainly depleted with the P-type substrate to form a vertical P–N junction, which improves the device BV. It also serves as the necessary current path when the device is in the on state. Ndrift also has great influence on the Ron,sp. It can be seen from the figure that when the Ndrift = 7 × 1015 cm−3, the BV and FOM of the DC DT SJ LDMOS reached the maximum. After the drift Ndrift reaches the optimal value, the P-type substrate is completely depleted, the BV of the DC DT SJ LDMOS device reaches the maximum value of 705.5 V.

Fig. 7.  (Color online) The influence of Ndrift on BV and FOM of Con. DT SJ LDMOS and DC DT SJ LDMOS.
DownLoad: Full-Size Img PowerPoint

In this part, the optimization process of key parameters that affects the performance of the device we proposed are shown as figures. In addition, the optimal value of each parameter is obtained. Compared with Con. DT SJ LDMOS, the charge imbalance problem of the Con. DT SJ LDMOS is solved by the double charge compensation layer. The electric field is modulated, and a higher BV is obtained. Compared with the Con. DT SJ LDMOS, the concentration of the drift region and SJ region of the new structure has been improved, and the conduction path is widened, which reduces the Ron,sp and achieves a much higher FOM.

The DC DT SJ LDMOS structure device with a double charge compensation layer is proposed for the problem of trench type SJ SIS capacitor in this paper. This section conducts a targeted study on the BV when the DC DT SJ LDMOS is in the off state and the Ron,sp in the on state, and compares the results of simulation to verify the principle of the device structure.

Fig. 8 shows the distribution of equipotential lines when the DC DT SJ LDMOS and Con. DT SJ LDMOS device are in the off state. Compared with the Con DT SJ LDMOS, the equipotential distribution of the new structure is denser, especially at the drain.

Fig. 8.  (Color online) The distribution of equipotential lines in the off state of (a) Con. DT SJ LDMOS, (b) DC DT SJ LDMOS.
DownLoad: Full-Size Img PowerPoint

Fig. 9 shows the surface electric field (Y = 0.01 μm) and the electric field (Y = 10 μm) of the body of the DC DT SJ LDMOS device and Con. DT SJ LDMOS device in the off state. From this figure, it can be seen that the surface electric and both the surface electric field and the bulk electric field of the proposed structure are higher than those of the Con. DT SJ LDMOS. The BV of the proposed structure is also higher than that of the Con. DT SJ LDMOS.

Fig. 9.  (Color online) The surface electric field (Y = 0.01 μm) and the electric field (Y = 10 μm) of the SJ region of the DC DT SJ LDMOS device and Con. DT SJ LDMOS device in the off state.
DownLoad: Full-Size Img PowerPoint

Fig. 10 shows the breakdown characteristic curve of DC DT SJ LDMOS and Con. DT SJ LDMOS in the off state and the output characteristic curve in the on state. It can be seen from the figure that the BV of DC DT SJ LDMOS is 705.5 V, which is higer than 549.5 V of Con. DT SJ LDMOS. The illustration in the Fig. 10 shows the output characteristic curves corresponding to the gate voltage 15 V of DC DT SJ LDMOS and the Con. DT SJ LDMOS respectively. It can be seen from this figure that both the on-state and off-state characteristics of the proposed structure are better than those of the Con. DT SJ LDMOS.

Fig. 10.  (Color online) Measured off-state breakdown curve and on-state Id–Vd curves with Vg = 15 V in the illustration of the TCCL DT SJ LDMOS and Con. DT SJ LDMOS.
DownLoad: Full-Size Img PowerPoint

Fig. 11 shows the relationships between BV and Ron,sp for Con. DT SJ LDMOS, some other reported structures[12-18] and DC DT SJ LDMOS proposed in this paper. From the figure it can be seen that the electrical performance of the device breaks through the “silicon limit”[11].

Fig. 11.  (Color online) The Ron,sp versus BV for different SJ LDMOSTs.
DownLoad: Full-Size Img PowerPoint

The SIS capacitor of deep trench SJ devices leads to charge imbalance in the SJ region. The DC DT SJ LDMOS is proposed in this paper to solve this problem, which adds a vertical variable doping compensation layer on the source side and an inverted triangular charge compensation layer on the drain based on the Con. DT SJ LDMOS. Moreover, the P–N–P dual voltage-resistant junction technology is used to improve the BV of the device. The double charge compensation layer solves the problem of the charge imbalance of the SJ region caused by the SIS capacitance. The P–N–P dual voltage-resistant junction technology adjusts the internal electric field, so that the BV of the device is improved. In addition, the current path is widen by the triangular-like SJ at the drain.

The simulation results show that compared with the Con. DT SJ LDMOS, the BV increases by 28.9% to 705.5 V, and the Ron,sp of the device is reduced by 50.2% to 23.7 mΩ·cm2 , and the FOM reached 21.0 MW/cm 2.



[1]
Coe D J. High voltage semiconductor device. United States Patent US 4754310, 1988
[2]
Chen X. Semiconductor power devices with alternating conductivity type high-voltage breakdown regions. United States Patent US 5216275, 1993
[3]
Zitouni M, Morancho F, Rossel P, et al. A new concept for the lateral DMOS transistor for smart power IC's. 11th International Symposium on Power Semiconductor Devices and ICs, 1999, 73 doi: 10.1109/ISPSD.1999.764055
[4]
Williams R K, Darwish M N, Blanchard R A, et al. The trench power MOSFET: Part I—History, technology, and prospects. IEEE Trans Electron Devices, 2017, 64, 674 doi: 10.1109/TED.2017.2653239
[5]
Theolier L, Mahfoz-Kotb H, Isoird K, et al. A new junction termination using a deep trench filled with BenzoCycloButene. IEEE Electron Device Lett, 2009, 30, 687 doi: 10.1109/LED.2009.2020348
[6]
Xia C, Cheng X H, Wang Z J, et al. Improvement of SOI trench LDMOS performance with double vertical metal field plate. IEEE Trans Electron Devices, 2014, 61, 3477 doi: 10.1109/TED.2014.2349553
[7]
Park J, Ko K, Eum J, et al. A proposal of LDMOS using Deep Trench poly field plate. 2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's, 2015, 149 doi: 10.1109/ISPSD.2015.7123411
[8]
Cao Z, Duan B X, Shi T T, et al. Theory analyses of SJ-LDMOS with multiple floating buried layers based on bulk electric field modulation. IEEE Trans Electron Devices, 2018, 65, 2565 doi: 10.1109/TED.2018.2827064
[9]
Cheng J J, Li P, Chen W Z, et al. Simulation study of a super-junction deep-trench LDMOS with a trapezoidal trench. IEEE J Electron Devices Soc, 2018, 6, 1091 doi: 10.1109/JEDS.2018.2867344
[10]
Zhou K, Luo X R, Li Z J, et al. Analytical model and new structure of the variable-k dielectric trench LDMOS with improved breakdown voltage and specific ON-resistance. IEEE Trans Electron Devices, 2015, 62, 3334 doi: 10.1109/TED.2015.2466694
[11]
Yang D, Hu S D, Lei J M, et al. An ultra-low specific on-resistance double-gate trench SOI LDMOS with P/N Pillars. Superlattices Microstruct, 2017, 112, 269 doi: 10.1016/j.spmi.2017.09.033
[12]
Cheng J J, Chen W Z, Li P. Improvement of deep-trench LDMOS with variation vertical doping for charge-balance super-junction. IEEE Trans Electron Devices, 2018, 65, 1404 doi: 10.1109/TED.2018.2802485
[13]
Iqbal M M H, Udrea F, Napoli E. On the static performance of the RESURF LDMOSFETS for power ICs. 2009 21st International Symposium on Power Semiconductor Devices & IC's, 2009, 247 doi: 10.1109/ISPSD.2009.5158048
[14]
Duan B X, Yuan S, Cao Z, et al. New superjunction LDMOS with the complete charge compensation by the electric field modulation. IEEE Electron Device Lett, 2014, 35, 1115 doi: 10.1109/LED.2014.2359293
[15]
Wang Y D, Duan B X, Zhang C, et al. AC-SJ VDMOS with ultra-low resistance. Micro Nano Lett, 2020, 15, 230 doi: 10.1049/mnl.2019.0497
[16]
Zhang W T, Wang R, Cheng S K, et al. Optimization and experiments of lateral semi-superjunction device based on normalized current-carrying capability. IEEE Electron Device Lett, 2019, 40, 1969 doi: 10.1109/LED.2019.2948198
[17]
Iwamoto S, Takahashi K, Kuribayashi H, et al. Above 500V class Superjunction MOSFETs fabricated by deep trench etching and epitaxial growth. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005, 31 doi: 10.1109/ISPSD.2005.1487943
[18]
Nautiyal P, Agrawal A, Kumari S, et al. Electrical characteristic investigation of variation vertical doping superjunction UMOS. 2019 IEEE 16th India Council International Conference, 2019, 1 doi: 10.1109/INDICON47234.2019.9030340
[19]
Kushwaha P K, Nautiyal P, Gupta A, et al. An improved SJ UMOS with modified gate electrode to reduce gate charge. 2019 9th Annual Information Technology, Electromechanical Engineering and Microelectronics Conference, 2019, 81 doi: 10.1109/IEMECONX.2019.8877004
[20]
Wu L J, Ding Q L, Chen J Q. Improved deep trench super-junction LDMOS breakdown voltage by shielded silicon-insulator-silicon capacitor. Silicon, 2021, 13, 3441 doi: 10.1007/s12633-020-00771-0
[21]
Chen W Z, He L J, Han Z S, et al. The simulation study of the SOI trench LDMOS with lateral super junction. IEEE J Electron Devices Soc, 2018, 6, 708 doi: 10.1109/JEDS.2018.2842236
Fig. 1.  (Color online) The structure of (a) DC DT SJ LDMOS and (b) Con. DT SJ LDMOS.

DownLoad: Full-Size Img PowerPoint
Fig. 2.  (Color online) Structure and composition of the DC DT SJ LDMOS.

DownLoad: Full-Size Img PowerPoint
Fig. 3.  (Color online) The influence of Nsj at source on BV of Con. DT SJ LDMOS and DC DT SJ LDMOS.

DownLoad: Full-Size Img PowerPoint
Fig. 4.  (Color online) The influence of Nsj2 at the drain on BV of DC DT SJ LDMOS.

DownLoad: Full-Size Img PowerPoint
Fig. 5.  (Color online) The influence of NTB at the drain on BV of DC DT SJ LDMOS.

DownLoad: Full-Size Img PowerPoint
Fig. 6.  (Color online) The influence of NVB on BV of DC DT SJ LDMOS. (a) Influence of NVB, max on BV of DC DT SJ LDMOS. (b) Influence of NVB,min on BV of DC DT SJ LDMOS.

DownLoad: Full-Size Img PowerPoint
Fig. 7.  (Color online) The influence of Ndrift on BV and FOM of Con. DT SJ LDMOS and DC DT SJ LDMOS.

DownLoad: Full-Size Img PowerPoint
Fig. 8.  (Color online) The distribution of equipotential lines in the off state of (a) Con. DT SJ LDMOS, (b) DC DT SJ LDMOS.

DownLoad: Full-Size Img PowerPoint
Fig. 9.  (Color online) The surface electric field (Y = 0.01 μm) and the electric field (Y = 10 μm) of the SJ region of the DC DT SJ LDMOS device and Con. DT SJ LDMOS device in the off state.

DownLoad: Full-Size Img PowerPoint
Fig. 10.  (Color online) Measured off-state breakdown curve and on-state Id–Vd curves with Vg = 15 V in the illustration of the TCCL DT SJ LDMOS and Con. DT SJ LDMOS.

DownLoad: Full-Size Img PowerPoint
Fig. 11.  (Color online) The Ron,sp versus BV for different SJ LDMOSTs.

DownLoad: Full-Size Img PowerPoint

Table 1.   Key parameters used in simulation.

ParameterSymbolDC DT SJ LDMOSCon. DT SJ LDMOSUnit
Width of SiO2 trenchWtrench1010μm
Width of PN pillarWsj22μm
Thickness of PN pillartsj1717μm
Thickness of drift regiontdrift22μm
Thickness of substratetsub3838μm
Doping concentration of N/P pillar at sourceND1/NA1(Nsj)OptimizedOptimizedcm–3
Doping concentration of triangular-like SJ N/P pillar at drainND2/NA2(Nsj2)OptimizedOptimizedcm–3
Doping concentration of inverted triangular charge compensation layerNTBOptimized–cm–3
Vertical variable doping concentrationNVBOptimized–cm–3
Doping concentration of N drift regionNdriftOptimizedOptimizedcm–3
DownLoad: CSV
[1]
Coe D J. High voltage semiconductor device. United States Patent US 4754310, 1988
[2]
Chen X. Semiconductor power devices with alternating conductivity type high-voltage breakdown regions. United States Patent US 5216275, 1993
[3]
Zitouni M, Morancho F, Rossel P, et al. A new concept for the lateral DMOS transistor for smart power IC's. 11th International Symposium on Power Semiconductor Devices and ICs, 1999, 73 doi: 10.1109/ISPSD.1999.764055
[4]
Williams R K, Darwish M N, Blanchard R A, et al. The trench power MOSFET: Part I—History, technology, and prospects. IEEE Trans Electron Devices, 2017, 64, 674 doi: 10.1109/TED.2017.2653239
[5]
Theolier L, Mahfoz-Kotb H, Isoird K, et al. A new junction termination using a deep trench filled with BenzoCycloButene. IEEE Electron Device Lett, 2009, 30, 687 doi: 10.1109/LED.2009.2020348
[6]
Xia C, Cheng X H, Wang Z J, et al. Improvement of SOI trench LDMOS performance with double vertical metal field plate. IEEE Trans Electron Devices, 2014, 61, 3477 doi: 10.1109/TED.2014.2349553
[7]
Park J, Ko K, Eum J, et al. A proposal of LDMOS using Deep Trench poly field plate. 2015 IEEE 27th International Symposium on Power Semiconductor Devices & IC's, 2015, 149 doi: 10.1109/ISPSD.2015.7123411
[8]
Cao Z, Duan B X, Shi T T, et al. Theory analyses of SJ-LDMOS with multiple floating buried layers based on bulk electric field modulation. IEEE Trans Electron Devices, 2018, 65, 2565 doi: 10.1109/TED.2018.2827064
[9]
Cheng J J, Li P, Chen W Z, et al. Simulation study of a super-junction deep-trench LDMOS with a trapezoidal trench. IEEE J Electron Devices Soc, 2018, 6, 1091 doi: 10.1109/JEDS.2018.2867344
[10]
Zhou K, Luo X R, Li Z J, et al. Analytical model and new structure of the variable-k dielectric trench LDMOS with improved breakdown voltage and specific ON-resistance. IEEE Trans Electron Devices, 2015, 62, 3334 doi: 10.1109/TED.2015.2466694
[11]
Yang D, Hu S D, Lei J M, et al. An ultra-low specific on-resistance double-gate trench SOI LDMOS with P/N Pillars. Superlattices Microstruct, 2017, 112, 269 doi: 10.1016/j.spmi.2017.09.033
[12]
Cheng J J, Chen W Z, Li P. Improvement of deep-trench LDMOS with variation vertical doping for charge-balance super-junction. IEEE Trans Electron Devices, 2018, 65, 1404 doi: 10.1109/TED.2018.2802485
[13]
Iqbal M M H, Udrea F, Napoli E. On the static performance of the RESURF LDMOSFETS for power ICs. 2009 21st International Symposium on Power Semiconductor Devices & IC's, 2009, 247 doi: 10.1109/ISPSD.2009.5158048
[14]
Duan B X, Yuan S, Cao Z, et al. New superjunction LDMOS with the complete charge compensation by the electric field modulation. IEEE Electron Device Lett, 2014, 35, 1115 doi: 10.1109/LED.2014.2359293
[15]
Wang Y D, Duan B X, Zhang C, et al. AC-SJ VDMOS with ultra-low resistance. Micro Nano Lett, 2020, 15, 230 doi: 10.1049/mnl.2019.0497
[16]
Zhang W T, Wang R, Cheng S K, et al. Optimization and experiments of lateral semi-superjunction device based on normalized current-carrying capability. IEEE Electron Device Lett, 2019, 40, 1969 doi: 10.1109/LED.2019.2948198
[17]
Iwamoto S, Takahashi K, Kuribayashi H, et al. Above 500V class Superjunction MOSFETs fabricated by deep trench etching and epitaxial growth. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005, 31 doi: 10.1109/ISPSD.2005.1487943
[18]
Nautiyal P, Agrawal A, Kumari S, et al. Electrical characteristic investigation of variation vertical doping superjunction UMOS. 2019 IEEE 16th India Council International Conference, 2019, 1 doi: 10.1109/INDICON47234.2019.9030340
[19]
Kushwaha P K, Nautiyal P, Gupta A, et al. An improved SJ UMOS with modified gate electrode to reduce gate charge. 2019 9th Annual Information Technology, Electromechanical Engineering and Microelectronics Conference, 2019, 81 doi: 10.1109/IEMECONX.2019.8877004
[20]
Wu L J, Ding Q L, Chen J Q. Improved deep trench super-junction LDMOS breakdown voltage by shielded silicon-insulator-silicon capacitor. Silicon, 2021, 13, 3441 doi: 10.1007/s12633-020-00771-0
[21]
Chen W Z, He L J, Han Z S, et al. The simulation study of the SOI trench LDMOS with lateral super junction. IEEE J Electron Devices Soc, 2018, 6, 708 doi: 10.1109/JEDS.2018.2842236
1

Analytical model for the effects of the variation of ferrolectric material parameters on the minimum subthreshold swing in negative capacitance capacitor

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    Lijuan Wu, Shaolian Su, Xing Chen, Jinsheng Zeng, Haifeng Wu. A deep trench super-junction LDMOS with double charge compensation layer[J]. Journal of Semiconductors, 2022, 43(10): 104102. doi: 10.1088/1674-4926/43/10/104102
    L J Wu, S L Su, X Chen, J S Zeng, H F Wu. A deep trench super-junction LDMOS with double charge compensation layer[J]. J. Semicond, 2022, 43(10): 104102. doi: 10.1088/1674-4926/43/10/104102
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    Received: 22 March 2022 Revised: 14 May 2022 Online: Uncorrected proof: 21 July 2022Corrected proof: 29 August 2022Published: 01 October 2022

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      Article Navigation >  Journal of Semiconductors  > 2022  >  43(10): 104102
      Lijuan Wu, Shaolian Su, Xing Chen, Jinsheng Zeng, Haifeng Wu. A deep trench super-junction LDMOS with double charge compensation layer[J]. Journal of Semiconductors, 2022, 43(10): 104102. doi: 10.1088/1674-4926/43/10/104102 ****L J Wu, S L Su, X Chen, J S Zeng, H F Wu. A deep trench super-junction LDMOS with double charge compensation layer[J]. J. Semicond, 2022, 43(10): 104102. doi: 10.1088/1674-4926/43/10/104102
      Citation:
      Lijuan Wu, Shaolian Su, Xing Chen, Jinsheng Zeng, Haifeng Wu. A deep trench super-junction LDMOS with double charge compensation layer[J]. Journal of Semiconductors, 2022, 43(10): 104102. doi: 10.1088/1674-4926/43/10/104102 ****
      L J Wu, S L Su, X Chen, J S Zeng, H F Wu. A deep trench super-junction LDMOS with double charge compensation layer[J]. J. Semicond, 2022, 43(10): 104102. doi: 10.1088/1674-4926/43/10/104102
      shu

      A deep trench super-junction LDMOS with double charge compensation layer

      DOI: 10.1088/1674-4926/43/10/104102

      • Hunan Provincial Key Laboratory of Flexible Electronic Materials Genome Engineering, School of Physics & Electronic Science, Changsha University of Science & Technology, Changsha 410114, China

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      • Lijuan Wu：received her B.S. from Sichuan University (SCU) in 2005 and Ph. D. Degree from the University of Electronic Science and Technology of China (UESTC) in 2012, respectively. Her graduate research work was focused on the high voltage drive structure and model. She is currently working on novel power device, process, and layout
      • Corresponding author: 305719669@qq.com
      • Received Date: 2022-03-22
      • Revised Date: 2022-05-14
        • Available Online: 2022-07-21

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