Simulation of MoS<sub>2</sub> stacked nanosheet field effect transistor

Yang Shen; He Tian; Tianling Ren

doi:10.1088/1674-4926/43/8/082002

J. Semicond. > 2022, Volume 43 > Issue 8 > 082002

ARTICLES

Simulation of MoS₂ stacked nanosheet field effect transistor

Yang Shen, He Tian and Tianling Ren

+ Author Affiliations

Corresponding author: He Tian, tianhe88@tsinghua.edu.cn; Tianling Ren, RenTL@tsinghua.edu.cn

DOI: 10.1088/1674-4926/43/8/082002

Abstract: Transition metal dichalcogenides are nowadays appealing to researchers for their excellent electronic properties. Vertical stacked nanosheet FET (NSFET) based on MoS₂ are proposed and studied by Poisson equation solver coupled with semi-classical quantum correction model implemented in Sentaurus workbench. It is found that, the 2D stacked NSFET can largely suppress short channel effects with improved subthreshold swing and drain induced barrier lowering, due to the excellent electrostatics of 2D MoS₂. In addition, small-signal capacitance is extracted and analyzed. The MoS₂ based NSFET shows great potential to enable next generation electronics.

Key words: MoS₂, stacked nanosheet GAA, TCAD simulation

References

[1]	Cui J, Chen L, Kang C L, et al. A high-linearity InGaP/GaAs HBT power amplifier for IEEE 802.11a/N. J Semicond, 2013, 34, 065001 doi: 10.1088/1674-4926/34/6/065001
[2]	Loubet N, Hook T, Montanini P, et al. Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET. 2017 Symposium on VLSI Technology, 2017, T230
[3]	Bansal A K, Jain I, Hook T B, et al. Series resistance reduction in stacked nanowire FETs for 7-nm CMOS technology. IEEE J Electron Devices Soc, 2016, 4, 266 doi: 10.1109/JEDS.2016.2592183
[4]	Radisavljevic B, Radenovic A, Brivio J, et al. Single-layer MoS₂ transistors. Nat Nanotechnol, 2011, 6, 147 doi: 10.1038/nnano.2010.279
[5]	Sebastian A, Pendurthi R, Choudhury T H, et al. Benchmarking monolayer MoS₂ and WS₂ field-effect transistors. Nat Commun, 2021, 12, 693 doi: 10.1038/s41467-020-20732-w
[6]	Das S, Sebastian A, Pop E, et al. Transistors based on two-dimensional materials for future integrated circuits. Nat Electron, 2021, 4, 786 doi: 10.1038/s41928-021-00670-1
[7]	Wu F, Tian H, Shen Y, et al. Vertical MoS₂ transistors with sub-1-nm gate lengths. Nature, 2022, 603, 259 doi: 10.1038/s41586-021-04323-3
[8]	Wang S, Liu X, Zhou P. The road for 2D semiconductors in the silicon age. Adv Mater, 2021, 2021, e2106886 doi: 10.1002/adma.202106886
[9]	Wu F, Ren J, Yang Y, et al. A 10 nm short channel MoS₂ transistor without the resolution requirement of photolithography. Adv Electron Mater, 2021, 7, 2170057 doi: 10.1002/aelm.202170057
[10]	Xie L, Liao M, Wang S, et al. Graphene-contacted ultrashort channel monolayer MoS₂ transistors. Adv Mater, 2017, 29, 1702522 doi: 10.1002/adma.201702522
[11]	Allain A, Kang J H, Banerjee K, et al. Electrical contacts to two-dimensional semiconductors. Nat Mater, 2015, 14, 1195 doi: 10.1038/nmat4452
[12]	Shen P C, Su C, Lin Y X, et al. Ultralow contact resistance between semimetal and monolayer semiconductors. Nature, 2021, 593, 211 doi: 10.1038/s41586-021-03472-9
[13]	Jariwala D, Sangwan V K, Late D J, et al. Band-like transport in high mobility unencapsulated single-layer MoS₂ transistors. Appl Phys Lett, 2013, 102, 173107 doi: 10.1063/1.4803920
[14]	Chen H W, Li J Y, Chen X Z, et al. Dramatic switching behavior in suspended MoS₂ field-effect transistors. Semicond Sci Technol, 2018, 33, 024001 doi: 10.1088/1361-6641/aaa222
[15]	Pon A, Carmel S, Bhattacharyya A, et al. Simulation of 2D layered material ballistic FETs using a hybrid methodology. 2019 IEEE International Conference on Electron Devices and Solid-State Circuits, 2019, 1 doi: 10.1109/EDSSC.2019.8754400
[16]	Sudarsanan A, Venkateswarlu S, Nayak K. Superior work function variability performance of horizontally stacked nanosheet FETs for sub-7-nm technology and beyond. 2020 4th IEEE Electron Devices Technology & Manufacturing Conference, 2020, 1 doi: 10.1109/EDTM47692.2020.9117974
[17]	Valasa S, Tayal S, Thoutam L R. Optimization of design space for vertically stacked junctionless nanosheet FET for analog/RF applications. Silicon, 2022, 1
[18]	Mohapatra E, Dash T P, Jena J, et al. Design study of gate-all-around vertically stacked nanosheet FETs for sub-7nm nodes. SN Appl Sci, 2021, 3, 540 doi: 10.1007/s42452-021-04539-y
[19]	Zebrev G I, Tselykovskiy A A, Batmanova D K, et al. Small-signal capacitance and current parameter modeling in large-scale high-frequency graphene field-effect transistors. IEEE Trans Electron Devices, 2013, 60, 1799 doi: 10.1109/TED.2013.2257793
[20]	Fang N, Nagashio K. Quantum-mechanical effect in atomically thin MoS₂ FET. 2D Mater, 2019, 7, 014001 doi: 10.1088/2053-1583/ab42c0

Fig. 1. (Color online) Energy band structures of MoS₂ unit cell simulated with DFT showing the high symmetry points and a band gap E_G = 1.78 eV.

DownLoad: Full-Size Img PowerPoint

Fig. 2. (Color online) (a) Schematic diagram of a 3-stacked NSFET. (b) Bird eye view and cross-sectional view along the channel of simulated structure in Sentaurus. (c) Simulation framework of this work. (d) Calibration of transfer curves to experimental data in log and linear form. Experimental data are from a 3-stacked NSFET (L_G = 10 nm).

DownLoad: Full-Size Img PowerPoint

Fig. 3. (Color online) Electrostatic performance comparison of Si and MoS₂ based 3-stacked NSFET. (a) Transfer characteristics. (b) Roll-off. (c) DIBL. (d) SS.

DownLoad: Full-Size Img PowerPoint

Fig. 4. (Color online) (a) Comparison of Si and MoS₂ based 3-stacked NSFET in terms of C_G–V_G characteristic. (b) C_G vs V_G with different sheet widths. (c) C_G vs V_G with different number of stacks. (d) C_G, C_GS, C_GD vs V_D, separately.

DownLoad: Full-Size Img PowerPoint

Table 1. Parameters used in this work.

E_G (eV)	Μ (cm²/(V·s))	m_e^*	m_h^*	T (nm)	χ (eV)	ε
1.78	100	~0.501m₀	~0.588m₀	0.65	4.2	4

DownLoad: CSV

[1]	Cui J, Chen L, Kang C L, et al. A high-linearity InGaP/GaAs HBT power amplifier for IEEE 802.11a/N. J Semicond, 2013, 34, 065001 doi: 10.1088/1674-4926/34/6/065001
[2]	Loubet N, Hook T, Montanini P, et al. Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET. 2017 Symposium on VLSI Technology, 2017, T230
[3]	Bansal A K, Jain I, Hook T B, et al. Series resistance reduction in stacked nanowire FETs for 7-nm CMOS technology. IEEE J Electron Devices Soc, 2016, 4, 266 doi: 10.1109/JEDS.2016.2592183
[4]	Radisavljevic B, Radenovic A, Brivio J, et al. Single-layer MoS₂ transistors. Nat Nanotechnol, 2011, 6, 147 doi: 10.1038/nnano.2010.279
[5]	Sebastian A, Pendurthi R, Choudhury T H, et al. Benchmarking monolayer MoS₂ and WS₂ field-effect transistors. Nat Commun, 2021, 12, 693 doi: 10.1038/s41467-020-20732-w
[6]	Das S, Sebastian A, Pop E, et al. Transistors based on two-dimensional materials for future integrated circuits. Nat Electron, 2021, 4, 786 doi: 10.1038/s41928-021-00670-1
[7]	Wu F, Tian H, Shen Y, et al. Vertical MoS₂ transistors with sub-1-nm gate lengths. Nature, 2022, 603, 259 doi: 10.1038/s41586-021-04323-3
[8]	Wang S, Liu X, Zhou P. The road for 2D semiconductors in the silicon age. Adv Mater, 2021, 2021, e2106886 doi: 10.1002/adma.202106886
[9]	Wu F, Ren J, Yang Y, et al. A 10 nm short channel MoS₂ transistor without the resolution requirement of photolithography. Adv Electron Mater, 2021, 7, 2170057 doi: 10.1002/aelm.202170057
[10]	Xie L, Liao M, Wang S, et al. Graphene-contacted ultrashort channel monolayer MoS₂ transistors. Adv Mater, 2017, 29, 1702522 doi: 10.1002/adma.201702522
[11]	Allain A, Kang J H, Banerjee K, et al. Electrical contacts to two-dimensional semiconductors. Nat Mater, 2015, 14, 1195 doi: 10.1038/nmat4452
[12]	Shen P C, Su C, Lin Y X, et al. Ultralow contact resistance between semimetal and monolayer semiconductors. Nature, 2021, 593, 211 doi: 10.1038/s41586-021-03472-9
[13]	Jariwala D, Sangwan V K, Late D J, et al. Band-like transport in high mobility unencapsulated single-layer MoS₂ transistors. Appl Phys Lett, 2013, 102, 173107 doi: 10.1063/1.4803920
[14]	Chen H W, Li J Y, Chen X Z, et al. Dramatic switching behavior in suspended MoS₂ field-effect transistors. Semicond Sci Technol, 2018, 33, 024001 doi: 10.1088/1361-6641/aaa222
[15]	Pon A, Carmel S, Bhattacharyya A, et al. Simulation of 2D layered material ballistic FETs using a hybrid methodology. 2019 IEEE International Conference on Electron Devices and Solid-State Circuits, 2019, 1 doi: 10.1109/EDSSC.2019.8754400
[16]	Sudarsanan A, Venkateswarlu S, Nayak K. Superior work function variability performance of horizontally stacked nanosheet FETs for sub-7-nm technology and beyond. 2020 4th IEEE Electron Devices Technology & Manufacturing Conference, 2020, 1 doi: 10.1109/EDTM47692.2020.9117974
[17]	Valasa S, Tayal S, Thoutam L R. Optimization of design space for vertically stacked junctionless nanosheet FET for analog/RF applications. Silicon, 2022, 1
[18]	Mohapatra E, Dash T P, Jena J, et al. Design study of gate-all-around vertically stacked nanosheet FETs for sub-7nm nodes. SN Appl Sci, 2021, 3, 540 doi: 10.1007/s42452-021-04539-y
[19]	Zebrev G I, Tselykovskiy A A, Batmanova D K, et al. Small-signal capacitance and current parameter modeling in large-scale high-frequency graphene field-effect transistors. IEEE Trans Electron Devices, 2013, 60, 1799 doi: 10.1109/TED.2013.2257793
[20]	Fang N, Nagashio K. Quantum-mechanical effect in atomically thin MoS₂ FET. 2D Mater, 2019, 7, 014001 doi: 10.1088/2053-1583/ab42c0

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Received: 13 March 2022 Revised: 07 June 2022 Online: Accepted Manuscript: 23 April 2022Uncorrected proof: 24 April 2022Published: 01 August 2022

Article Navigation > Journal of Semiconductors > 2022 > 43(8): 082002

Yang Shen, He Tian, Tianling Ren. Simulation of MoS2 stacked nanosheet field effect transistor[J]. Journal of Semiconductors, 2022, 43(8): 082002. doi: 10.1088/1674-4926/43/8/082002 ****Yang Shen, He Tian, Tianling Ren, Simulation of MoS2 stacked nanosheet field effect transistor[J]. Journal of Semiconductors, 2022, 43(8), 082002 doi: 10.1088/1674-4926/43/8/082002

Citation:

Yang Shen, He Tian, Tianling Ren. Simulation of MoS₂ stacked nanosheet field effect transistor[J]. Journal of Semiconductors, 2022, 43(8): 082002. doi: 10.1088/1674-4926/43/8/082002 ****

Yang Shen, He Tian, Tianling Ren, Simulation of MoS₂ stacked nanosheet field effect transistor[J]. Journal of Semiconductors, 2022, 43(8), 082002 doi: 10.1088/1674-4926/43/8/082002

Citation:

Yang Shen, He Tian, Tianling Ren. Simulation of MoS₂ stacked nanosheet field effect transistor[J]. Journal of Semiconductors, 2022, 43(8): 082002. doi: 10.1088/1674-4926/43/8/082002 ****

Yang Shen, He Tian, Tianling Ren, Simulation of MoS₂ stacked nanosheet field effect transistor[J]. Journal of Semiconductors, 2022, 43(8), 082002 doi: 10.1088/1674-4926/43/8/082002

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Simulation of MoS₂ stacked nanosheet field effect transistor

DOI: 10.1088/1674-4926/43/8/082002

School of Integrated Circuits and Beijing National Research Center for Information Science and Technology (BNRist), Tsinghua University, Beijing 100084, China

More Information

Yang Shen：received his B.S. degree from Hefei University of Technology in 2019. He is currently a PhD student under the supervision of Prof. He Tian at the School of Integrated Circuits, Tsinghua University. Her research focuses on devices based on 2D materials
He Tian：received the Ph.D. degree from the Institute of Microelectronics, Tsinghua University, in 2015. He is currently an associate professor in Tsinghua University. He was a recipient of the National Science Foundation for outstanding young scholars. He has co-authored over 100 papers and has over 5000 citations. He has been researching on various 2D materials-based novel nanodevices
Tianling Ren：received his Ph.D. degree in solid-state physics from the Department of Modern Applied Physics, Tsinghua University, Beijing, China, in 1997, where he has been a Full Professor with the Institute of Microelectronics since 2003. His main research interests include 2D material-based devices and novel nanoelectronic devices, intelligent sensors and integrated micro-electromechanical systems, and critical technology for advanced micro- and nanoelectronic
Corresponding author: tianhe88@tsinghua.edu.cn; RenTL@tsinghua.edu.cn
Received Date: 2022-03-13
Revised Date: 2022-06-07

Available Online: 2022-04-23

Abstract

Abstract

Transition metal dichalcogenides are nowadays appealing to researchers for their excellent electronic properties. Vertical stacked nanosheet FET (NSFET) based on MoS₂ are proposed and studied by Poisson equation solver coupled with semi-classical quantum correction model implemented in Sentaurus workbench. It is found that, the 2D stacked NSFET can largely suppress short channel effects with improved subthreshold swing and drain induced barrier lowering, due to the excellent electrostatics of 2D MoS₂. In addition, small-signal capacitance is extracted and analyzed. The MoS₂ based NSFET shows great potential to enable next generation electronics.
- MoS₂,
- stacked nanosheet GAA,
- TCAD simulation

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References(20)

References

[1]	Cui J, Chen L, Kang C L, et al. A high-linearity InGaP/GaAs HBT power amplifier for IEEE 802.11a/N. J Semicond, 2013, 34, 065001 doi: 10.1088/1674-4926/34/6/065001
[2]	Loubet N, Hook T, Montanini P, et al. Stacked nanosheet gate-all-around transistor to enable scaling beyond FinFET. 2017 Symposium on VLSI Technology, 2017, T230
[3]	Bansal A K, Jain I, Hook T B, et al. Series resistance reduction in stacked nanowire FETs for 7-nm CMOS technology. IEEE J Electron Devices Soc, 2016, 4, 266 doi: 10.1109/JEDS.2016.2592183
[4]	Radisavljevic B, Radenovic A, Brivio J, et al. Single-layer MoS₂ transistors. Nat Nanotechnol, 2011, 6, 147 doi: 10.1038/nnano.2010.279
[5]	Sebastian A, Pendurthi R, Choudhury T H, et al. Benchmarking monolayer MoS₂ and WS₂ field-effect transistors. Nat Commun, 2021, 12, 693 doi: 10.1038/s41467-020-20732-w
[6]	Das S, Sebastian A, Pop E, et al. Transistors based on two-dimensional materials for future integrated circuits. Nat Electron, 2021, 4, 786 doi: 10.1038/s41928-021-00670-1
[7]	Wu F, Tian H, Shen Y, et al. Vertical MoS₂ transistors with sub-1-nm gate lengths. Nature, 2022, 603, 259 doi: 10.1038/s41586-021-04323-3
[8]	Wang S, Liu X, Zhou P. The road for 2D semiconductors in the silicon age. Adv Mater, 2021, 2021, e2106886 doi: 10.1002/adma.202106886
[9]	Wu F, Ren J, Yang Y, et al. A 10 nm short channel MoS₂ transistor without the resolution requirement of photolithography. Adv Electron Mater, 2021, 7, 2170057 doi: 10.1002/aelm.202170057
[10]	Xie L, Liao M, Wang S, et al. Graphene-contacted ultrashort channel monolayer MoS₂ transistors. Adv Mater, 2017, 29, 1702522 doi: 10.1002/adma.201702522
[11]	Allain A, Kang J H, Banerjee K, et al. Electrical contacts to two-dimensional semiconductors. Nat Mater, 2015, 14, 1195 doi: 10.1038/nmat4452
[12]	Shen P C, Su C, Lin Y X, et al. Ultralow contact resistance between semimetal and monolayer semiconductors. Nature, 2021, 593, 211 doi: 10.1038/s41586-021-03472-9
[13]	Jariwala D, Sangwan V K, Late D J, et al. Band-like transport in high mobility unencapsulated single-layer MoS₂ transistors. Appl Phys Lett, 2013, 102, 173107 doi: 10.1063/1.4803920
[14]	Chen H W, Li J Y, Chen X Z, et al. Dramatic switching behavior in suspended MoS₂ field-effect transistors. Semicond Sci Technol, 2018, 33, 024001 doi: 10.1088/1361-6641/aaa222
[15]	Pon A, Carmel S, Bhattacharyya A, et al. Simulation of 2D layered material ballistic FETs using a hybrid methodology. 2019 IEEE International Conference on Electron Devices and Solid-State Circuits, 2019, 1 doi: 10.1109/EDSSC.2019.8754400
[16]	Sudarsanan A, Venkateswarlu S, Nayak K. Superior work function variability performance of horizontally stacked nanosheet FETs for sub-7-nm technology and beyond. 2020 4th IEEE Electron Devices Technology & Manufacturing Conference, 2020, 1 doi: 10.1109/EDTM47692.2020.9117974
[17]	Valasa S, Tayal S, Thoutam L R. Optimization of design space for vertically stacked junctionless nanosheet FET for analog/RF applications. Silicon, 2022, 1
[18]	Mohapatra E, Dash T P, Jena J, et al. Design study of gate-all-around vertically stacked nanosheet FETs for sub-7nm nodes. SN Appl Sci, 2021, 3, 540 doi: 10.1007/s42452-021-04539-y
[19]	Zebrev G I, Tselykovskiy A A, Batmanova D K, et al. Small-signal capacitance and current parameter modeling in large-scale high-frequency graphene field-effect transistors. IEEE Trans Electron Devices, 2013, 60, 1799 doi: 10.1109/TED.2013.2257793
[20]	Fang N, Nagashio K. Quantum-mechanical effect in atomically thin MoS₂ FET. 2D Mater, 2019, 7, 014001 doi: 10.1088/2053-1583/ab42c0

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Simulation of MoS₂ stacked nanosheet field effect transistor

Simulation of MoS₂ stacked nanosheet field effect transistor