J. Semicond. > 2022, Volume 43 > Issue 8 > 082801

ARTICLES

Demonstration of 4H-SiC CMOS digital IC gates based on the mainstream 6-inch wafer processing technique

Tongtong Yang1, Yan Wang1, 2, and Ruifeng Yue1, 2

+ Author Affiliations

 Corresponding author: Yan Wang, wangy46@tsinghua.edu.cn

DOI: 10.1088/1674-4926/43/8/082801

PDF

Turn off MathJax

Abstract: In this article, the design, fabrication and characterization of silicon carbide (SiC) complementary-metal-oxide-semiconductor (CMOS)-based integrated circuits (ICs) are presented. A metal interconnect strategy is proposed to fabricate the fundamental N-channel MOS (NMOS) and P-channel MOS (PMOS) devices that are required for the CMOS circuit configuration. Based on the mainstream 6-inch SiC wafer processing technology, the simultaneous fabrication of SiC CMOS ICs and power MOSFET is realized. Fundamental gates, such as inverter and NAND gates, are fabricated and tested. The measurement results show that the inverter and NAND gates function well. The calculated low-to-high delay (low-to-high output transition) and high-to-low delay (high-to-low output transition) are 49.9 and 90 ns, respectively.

Key words: SiCCMOSintegrated circuitinverterNANDmetal interconnect

Although silicon carbide (SiC) power devices have been proven to be stable and reliable for high temperature operation, the present control and drive circuits are based on silicon material, which restricts the maximum operating temperature of the power electronics system[1]. Developing SiC integrated circuits (ICs) is beneficial for realizing the full potential of SiC material in high temperature applications[2-6]. Compared with other technology, the complementary-metal-oxide-semiconductor (CMOS) technology could achieve full rail-to-rail output voltage switching, low power losses and temperature-independent logic levels[7, 8]. Unfortunately, the reported SiC CMOS ICs in the literature are fabricated using specially developed technology, which is not compatible with the mainstream 4H-SiC power device processing technology.

Motivated by developing 4H-SiC based power ICs which integrates the control circuits and power device in a single chip, this article reports the implementation of fundamental CMOS-based digital gates based on 6-inch SiC wafer processing technology, in which the digital gates and power devices are fabricated simultaneously. The fundamental characteristics of the inverter and NAND gates are characterized and analyzed. The experimental results that are obtained by this work will serve as useful guides for driving the development of SiC-based power ICs.

The CMOS circuit requires both N-channel MOS (NMOS) and P-channel MOS (PMOS) devices. To implement the SiC NMOS and PMOS while ensuring compatibility with the SiC power device processing technology, the CMOS configuration in Fig. 1 is adopted [7, 8]. The PMOS is formed directly in the drift layer, while the NMOS is fabricated in a P-well. The P-well also functions as a base layer for the SiC power MOSFET.

Fig. 1.  (Color online) The CMOS circuit configuration that is used in this work

In fabricating the SiC power MOSFET, only one thick metal is used for the cell interconnect [9]. In this work, a metal interconnect strategy is proposed to implement the CMOS circuits. The proposed metal interconnect strategy is shown in Fig. 2. The polysilicon acts as the gate (G) and the ohmic metal is extended to the other side to form the source (S), as shown in Figs. 2(a) and 2(b), respectively. After depositing the interlayer dielectric, contact holes are etched, as shown in Fig. 2(c). After sputtering the thick Aluminum metal, the wet etching technique is used to form the three electrodes, as shown in Fig. 2(d). The fabrications of SiC NMOS and PMOS are thus finished. The channel length for both NMOS and PMOS is 2 μm. The gate oxide thickness is 50 nm.

Fig. 2.  (Color online) The proposed metal interconnect strategy for fabricating the SiC NMOS and PMOS devices.

High temperature and high energy aluminum implantations and nitrogen implantations are used to form the P-wells, P+ regions and N+ regions, respectively. The process conditions for the implantations are summarized in Table 1. The obtained doping profiles for these regions are shown in Fig. 3. The depth of P-well should be larger than that of N+ region because the NMOS is located in the P-well.

Table 1.  The temperature, dose and energy used in the fabrications for P-well, P+ region and N+ regions.
ItemTemperature (°C)Energy (keV)
P-well500550
500360
500200
P+500320
500200
50040
N+500160
500130
50040
DownLoad: CSV  | Show Table
Fig. 3.  (Color online) The doping profiles of N+, P-well and P+ regions obtained by process simulations through Synopsys Sentaurus.

Based on the mainstream 6-inch SiC wafer processing technology, we realized the simultaneous fabrication of SiC digital gates and a SiC power MOSFET. Fig. 4 gives the photos of the fabricated SiC NMOS, PMOS and the CMOS gates. As shown in Figs. 4(a) and 4(b), the drain (D), gate (G) and source (S) of the NMOS and PMOS are clearly distinguished. The Inverter gate shown in Fig. 4(c) contains both PMOS and NMOS device, and the NAND gate in Fig. 4(d) integrates four devices. The measured transfer characteristics of the PMOS and NMOS are shown in Fig. 5. The typical threshold voltage Vth of the PMOS is 8.2 V while that of the NMOS is only 2.1 V. The asymmetry of Vth between PMOS and NMOS should be attributed to the unavoidable fixed charges located at the interface of SiC and SiO2[10].

Fig. 4.  (Color online) The fabricated SiC NMOS, PMOS and CMOS gates. (a) PMOS. (b) NMOS. (c) Inverter gate. (d) NAND gate.
Fig. 5.  (Color online) The measured transfer characteristics of the PMOS and NMOS.

After bonding the fabricated inverter and NAND gates, the functions of the two gates are evaluated. The measured voltage transfer curves of the inverter gate at various VDDs are shown in Fig. 6(a). The inverter gate functions are as expected. We also extract the inverter gain from the voltage transfer curves and the results are shown in Fig. 6(b). It is found that the inverter gain increases with VDD. At a VDD of 15 V, the inverter gain is larger than 50, which is beneficial for fabricating more complex integrated circuits, such as a multi-stage ring oscillator.

Fig. 6.  (Color online) (a) The typical measured voltage transfer curves and (b) the extracted inverter gain of the fabricated Inverter gate.

Fig. 7 give the typical measured input-output voltage curves of the inverter gate. The obtained waveform demonstrates that the inverter gate functions well. In addition, from the voltage curves, the calculated low-to-high delay tpLH (low-to-high output transition) and high-to-low delay tpHL (high-to-low output transition) are 49.9 and 90 ns, respectively. The measured dynamic switching characteristic of the NAND gate is shown in Fig. 8. Obviously, the obtained results verify the normal operation of the NAND gate.

Fig. 7.  (Color online) The measured switching input-output characteristics of the fabricated SiC Inverter gate.
Fig. 8.  (Color online) The measured switching input-output characteristics of the fabricated SiC NAND gate.

The fabricated SiC power MOSFET is of a trench structure. The related experimental results have been reported in Ref. [11]. Based on the proposed metal interconnect strategy, the SiC IC gates and trench power MOSFET are fabricated on the same wafer. It is expected that SiC power ICs which integrate the SiC ICs and a power MOSFET will be realized in future work.

In this article, 4H-SiC CMOS digital gates are successfully fabricated based on the mainstream SiC processing technology. The functions of the inverter and NAND gate are verified through experimental measurements. Based on these fundamental gates, more complex SiC CMOS based integrated circuits can be fabricated. Moreover, the simultaneous fabrication of the SiC CMOS circuits and power MOSFET can be realized. Therefore, the results of this research can provide valuable guides for the future fabrication of power integrated circuits to realize the full potential of SiC power devices in high temperature applications.

The authors would like to thank State Key Laboratory of Advanced Power Transmission Technology, Global Energy Interconnection Research Institute Co. Ltd. for the fabrication of the SiC trench MOSFET and Datang Microelectronics Technology limited Company for wafer dicing.



[1]
Murphree R C, Roy S, Ahmed S, et al. A SiC CMOS linear voltage regulator for high-temperature applications. IEEE Trans Power Electron, 2020, 35, 913 doi: 10.1109/TPEL.2019.2914169
[2]
Lanni L, Malm B G, Östling M, et al. 500 °C bipolar integrated OR/NOR gate in 4H-SiC. IEEE Electron Device Lett, 2013, 34, 1091 doi: 10.1109/LED.2013.2272649
[3]
Kashyap A S, Chen C P, Ghandi R, et al. Silicon carbide integrated circuits for extreme environments. The 1st IEEE Workshop on Wide Bandgap Power Devices and Applications, 2013, 60 doi: 10.1109/WiPDA.2013.6695562
[4]
Lee J Y, Singh S, Cooper J A. Demonstration and characterization of bipolar monolithic integrated circuits in 4H-SiC. IEEE Trans Electron Devices, 2008, 55, 1946 doi: 10.1109/TED.2008.926681
[5]
Sheng K, Zhang Y X, Su M, et al. Demonstration of the first SiC power integrated circuit. Solid State Electron, 2008, 52, 1636 doi: 10.1016/j.sse.2008.06.037
[6]
Alexandru M, Banu V, Jorda X, et al. SiC integrated circuit control electronics for high-temperature operation. IEEE Trans Ind Electron, 2015, 62, 3182 doi: 10.1109/TIE.2014.2379212
[7]
Ryu S H, Kornegay K T, Cooper J A, et al. Digital CMOS IC's in 6H-SiC operating on a 5-V power supply. IEEE Trans Electron Devices, 1998, 45, 45 doi: 10.1109/16.658810
[8]
Okamoto M, Yao A, Sato H, et al. First demonstration of a monolithic SiC power IC integrating a vertical MOSFET with a CMOS gate buffer. 2021 33rd International Symposium on Power Semiconductor Devices and ICs, 2021, 71 doi: 10.23919/ISPSD50666.2021.9452262
[9]
Huang R H, Tao Y H, Bai S, et al. Design and fabrication of a 3.3 kV 4H-SiC MOSFET. J Semicond, 2015, 36, 094002 doi: 10.1088/1674-4926/36/9/094002
[10]
Licciardo G D, di Benedetto L, Bellone S. Modeling of the SiO2/SiC interface-trapped charge as a function of the surface potential in 4H-SiC vertical-DMOSFET. IEEE Trans Electron Devices, 2016, 63, 1783 doi: 10.1109/TED.2016.2531796
[11]
Yang T T, Li X B, Wang Y, et al. Design and fabrication of 860V SiC trench MOSFET with stripe and rectangular cells. 2021 IEEE International Conference on Integrated Circuits, Technologies and Applications, 2021, 161
Fig. 1.  (Color online) The CMOS circuit configuration that is used in this work

Fig. 2.  (Color online) The proposed metal interconnect strategy for fabricating the SiC NMOS and PMOS devices.

Fig. 3.  (Color online) The doping profiles of N+, P-well and P+ regions obtained by process simulations through Synopsys Sentaurus.

Fig. 4.  (Color online) The fabricated SiC NMOS, PMOS and CMOS gates. (a) PMOS. (b) NMOS. (c) Inverter gate. (d) NAND gate.

Fig. 5.  (Color online) The measured transfer characteristics of the PMOS and NMOS.

Fig. 6.  (Color online) (a) The typical measured voltage transfer curves and (b) the extracted inverter gain of the fabricated Inverter gate.

Fig. 7.  (Color online) The measured switching input-output characteristics of the fabricated SiC Inverter gate.

Fig. 8.  (Color online) The measured switching input-output characteristics of the fabricated SiC NAND gate.

Table 1.   The temperature, dose and energy used in the fabrications for P-well, P+ region and N+ regions.

ItemTemperature (°C)Energy (keV)
P-well500550
500360
500200
P+500320
500200
50040
N+500160
500130
50040
DownLoad: CSV
[1]
Murphree R C, Roy S, Ahmed S, et al. A SiC CMOS linear voltage regulator for high-temperature applications. IEEE Trans Power Electron, 2020, 35, 913 doi: 10.1109/TPEL.2019.2914169
[2]
Lanni L, Malm B G, Östling M, et al. 500 °C bipolar integrated OR/NOR gate in 4H-SiC. IEEE Electron Device Lett, 2013, 34, 1091 doi: 10.1109/LED.2013.2272649
[3]
Kashyap A S, Chen C P, Ghandi R, et al. Silicon carbide integrated circuits for extreme environments. The 1st IEEE Workshop on Wide Bandgap Power Devices and Applications, 2013, 60 doi: 10.1109/WiPDA.2013.6695562
[4]
Lee J Y, Singh S, Cooper J A. Demonstration and characterization of bipolar monolithic integrated circuits in 4H-SiC. IEEE Trans Electron Devices, 2008, 55, 1946 doi: 10.1109/TED.2008.926681
[5]
Sheng K, Zhang Y X, Su M, et al. Demonstration of the first SiC power integrated circuit. Solid State Electron, 2008, 52, 1636 doi: 10.1016/j.sse.2008.06.037
[6]
Alexandru M, Banu V, Jorda X, et al. SiC integrated circuit control electronics for high-temperature operation. IEEE Trans Ind Electron, 2015, 62, 3182 doi: 10.1109/TIE.2014.2379212
[7]
Ryu S H, Kornegay K T, Cooper J A, et al. Digital CMOS IC's in 6H-SiC operating on a 5-V power supply. IEEE Trans Electron Devices, 1998, 45, 45 doi: 10.1109/16.658810
[8]
Okamoto M, Yao A, Sato H, et al. First demonstration of a monolithic SiC power IC integrating a vertical MOSFET with a CMOS gate buffer. 2021 33rd International Symposium on Power Semiconductor Devices and ICs, 2021, 71 doi: 10.23919/ISPSD50666.2021.9452262
[9]
Huang R H, Tao Y H, Bai S, et al. Design and fabrication of a 3.3 kV 4H-SiC MOSFET. J Semicond, 2015, 36, 094002 doi: 10.1088/1674-4926/36/9/094002
[10]
Licciardo G D, di Benedetto L, Bellone S. Modeling of the SiO2/SiC interface-trapped charge as a function of the surface potential in 4H-SiC vertical-DMOSFET. IEEE Trans Electron Devices, 2016, 63, 1783 doi: 10.1109/TED.2016.2531796
[11]
Yang T T, Li X B, Wang Y, et al. Design and fabrication of 860V SiC trench MOSFET with stripe and rectangular cells. 2021 IEEE International Conference on Integrated Circuits, Technologies and Applications, 2021, 161
1

Influence of the Trapping Effect on Temperature Characteristics in 4H-SiC MESFETs

Lü Hongliang, Zhang Yimen, Zhang Yuming, Che Yong, Wang Yuehu, et al.

Journal of Semiconductors, 2008, 29(2): 334-337.

2

Transient Characteristic Analysis of a Double-Gate Dual-Strained-Channel SOI CMOS

Sun Liwei, Gao Yong, Yang Yuan, Liu Jing

Journal of Semiconductors, 2008, 29(8): 1566-1569.

3

Analysis and Modeling of Broadband CMOS Monolithic Balun up to Millimeter-Wave Frequencies

Xia Jun, Wang Zhigong, Wu Xiushan, Li Wei

Journal of Semiconductors, 2008, 29(3): 467-472.

4

A Novel CMOS Current Mode Bandgap Reference

Xing Xinpeng, Li Dongmei, Wang Zhihua

Journal of Semiconductors, 2008, 29(7): 1249-1253.

5

A Monolithic Integrated CMOS Thermal Vacuum Sensor

Zhang Fengtian, Tang Zhen'an, Wang Jiaqi, Yu Jun

Journal of Semiconductors, 2008, 29(6): 1103-1107.

6

A High Speed,12-Channel Parallel,Monolithic IntegratedCMOS OEIC Receiver

Zhu Haobo, Mao Luhong, Yu Changliang, Chen Hongda, Tang Jun, et al.

Chinese Journal of Semiconductors , 2007, 28(9): 1341-1345.

7

Gas Fluid Modeling of SiC Epitaxial Growth in Chemical Vapor Deposition Processes

Jia Renxu, Zhang Yimen, Zhang Yuming, Guo Hui

Chinese Journal of Semiconductors , 2007, 28(S1): 541-544.

8

Recent Progress in SiC Monocrystal Growth and Wafer Machining

Jiang Shouzhen, Xu Xian'gang, Li Juan, Chen Xiufang, Wang Yingmin, et al.

Chinese Journal of Semiconductors , 2007, 28(5): 810-814.

9

Structural Analysis of the SiCGe Epitaxial Layer Grown on SiC Substrate

Li Lianbi, Chen Zhiming, Pu Hongbin, Lin Tao, Li Jia, et al.

Chinese Journal of Semiconductors , 2007, 28(S1): 123-126.

10

Design and Implementation of an Optoelectronic Integrated Receiver in Standard CMOS Process

Yu Changliang, Mao Luhong, Song Ruiliang, Zhu Haobo, Wang Rui, et al.

Chinese Journal of Semiconductors , 2007, 28(8): 1198-1203.

11

Mo/Schottky Barrier Diodes on 4H-Silicon Carbide

Zhang Fasheng, Li Xinran

Chinese Journal of Semiconductors , 2007, 28(3): 435-438.

12

Concept and Simulation of a Novel Pre-Equalized CMOS Optoelectronic Integrated Receiver

Yu Changliang, Mao Luhong, Zhu Haobo, Song Ruiliang, Chen Mingyi, et al.

Chinese Journal of Semiconductors , 2007, 28(6): 951-957.

13

Sensitivity Design for a CMOS Optoelectronic Integrated Circuit Receiver

Zhu Haobo, Mao Luhong, Yu Changliang, Ma Liyuan

Chinese Journal of Semiconductors , 2007, 28(5): 676-680.

14

Design and Simulation of a Light-Activated Darlington Transistor Based on a SiCGe/3C-SiC Hetero-Structure

Chen Zhiming, Ren Ping, Pu Hongbin

Chinese Journal of Semiconductors , 2006, 27(2): 254-257.

15

Ohmic Contact on SiC Using n+ Polysilicon/n+ SiC Heterojunction

Zhang Lin, Zhang Yimen, Zhang Yuming, Tang Xiaoyan

Chinese Journal of Semiconductors , 2006, 27(S1): 378-380.

16

An Integrated Four Quadrant CMOS Analog Multiplier

Huo Mingxue, Tan Xiaoyun, Liu Xiaowei, Wang Yonggang, Ren Lianfeng, et al.

Chinese Journal of Semiconductors , 2006, 27(S1): 335-339.

17

C-V Characteristic Distortion in the Pinch-Off Mode of a Buried Channel MOS Structure in 4H-SiC

Gao Jinxia, Zhang Yimen, Zhang Yuming

Chinese Journal of Semiconductors , 2006, 27(7): 1259-1263.

18

LPCVD Homoepitaxial Growth on Off-Axis Si-Face 4H-SiC(0001) Substrates

Wang Lei, Sun Guosheng, Gao Xin, Zhao Wanshun, Zhang Yongxing, et al.

Chinese Journal of Semiconductors , 2005, 26(S1): 113-116.

19

Turn-On Mechanism of a Light-Activated SiC Heterojuntion Darlington HBT

Pu Hongbin, Chen Zhiming

Chinese Journal of Semiconductors , 2005, 26(S1): 143-146.

20

Measurements of Optical Characterization for CMOS

Song Min, Zheng Yaru, Lu Yongjun, Qu Yanling, Song Limin, et al.

Chinese Journal of Semiconductors , 2005, 26(12): 2407-2410.

1. Chen, H., Liu, A., Huang, R. et al. Design and Manufacturing of 4H‑SiC CMOS High Temperature Integrated Circuits | [4H-SiC CMOS高温集成电路设计与制造]. Guti Dianzixue Yanjiu Yu Jinzhan/Research and Progress of Solid State Electronics, 2024, 44(2): 109-112 and 118. doi:10.12450/j.gtdzx.2024.02.002
  • Search

    Advanced Search >>

    GET CITATION

    Tongtong Yang, Yan Wang, Ruifeng Yue. Demonstration of 4H-SiC CMOS digital IC gates based on the mainstream 6-inch wafer processing technique[J]. Journal of Semiconductors, 2022, 43(8): 082801. doi: 10.1088/1674-4926/43/8/082801
    T T Yang, Y Wang, R F Yue. Demonstration of 4H-SiC CMOS digital IC gates based on the mainstream 6-inch wafer processing technique[J]. J. Semicond, 2022, 43(8): 082801. doi: 10.1088/1674-4926/43/8/082801
    shu

    Export: BibTex EndNote

    Article Metrics

    Article views: 2337 Times PDF downloads: 210 Times Cited by: 1 Times

    History

    Received: 28 February 2022 Revised: 03 April 2022 Online: Accepted Manuscript: 24 May 2022Uncorrected proof: 25 May 2022Published: 01 August 2022

    Catalog

      Email This Article

      User name:
      Email:*请输入正确邮箱
      Code:*验证码错误
      Tongtong Yang, Yan Wang, Ruifeng Yue. Demonstration of 4H-SiC CMOS digital IC gates based on the mainstream 6-inch wafer processing technique[J]. Journal of Semiconductors, 2022, 43(8): 082801. doi: 10.1088/1674-4926/43/8/082801 ****T T Yang, Y Wang, R F Yue. Demonstration of 4H-SiC CMOS digital IC gates based on the mainstream 6-inch wafer processing technique[J]. J. Semicond, 2022, 43(8): 082801. doi: 10.1088/1674-4926/43/8/082801
      Citation:
      Tongtong Yang, Yan Wang, Ruifeng Yue. Demonstration of 4H-SiC CMOS digital IC gates based on the mainstream 6-inch wafer processing technique[J]. Journal of Semiconductors, 2022, 43(8): 082801. doi: 10.1088/1674-4926/43/8/082801 ****
      T T Yang, Y Wang, R F Yue. Demonstration of 4H-SiC CMOS digital IC gates based on the mainstream 6-inch wafer processing technique[J]. J. Semicond, 2022, 43(8): 082801. doi: 10.1088/1674-4926/43/8/082801

      Demonstration of 4H-SiC CMOS digital IC gates based on the mainstream 6-inch wafer processing technique

      DOI: 10.1088/1674-4926/43/8/082801
      More Information
      • Tongtong Yang:is currently pursuing a Ph.D. degree at the School of Integrated Circuits, Tsinghua University, Beijing, China. His research interests include the design, fabrication and modeling of SiC power devices
      • Yan Wang:is a professor with the School of Integrated Circuits, Tsinghua University, Beijing, China. Her current research interests include the design of RF and MM-wave applications, and the modeling of SiC power devices
      • Ruifeng Yue:is a professor with the School of Integrated Circuits, Tsinghua University, Beijing, China. His current research interests include the design and fabrication of SiC power devices
      • Corresponding author: wangy46@tsinghua.edu.cn
      • Received Date: 2022-02-28
      • Revised Date: 2022-04-03
      • Available Online: 2022-05-24

      Catalog

        /

        DownLoad:  Full-Size Img  PowerPoint
        Return
        Return