J. Semicond. > 2008, Volume 29 > Issue 10 > 1917-1921

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A Novel 4T nMOS-Only SRAM Cell in 32nm Technology Node

Zhang Wancheng and Wu Nanjian

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Abstract: This paper proposes a novel loadless 4T SRAM cell composed of nMOS transistors.The SRAM cell is based on 32nm silicon-on-insulator (SOI) technology node.It consists of two access transistors and two pull-down transistors.The pull-down transistors have larger channel length than the access transistors.Due to the significant short channel effect of small-size MOS transistors,the access transistors have much larger leakage current than the pull-down transistors,enabling the SRAM cell to maintain logic "1" while in standby.The storage node voltages of the cell are fed back to the back-gates of the access transistors,enabling the stable "read" operation of the cell.The use of back-gate feedback also helps to improve the static noise margin (SNM) of the cell.The proposed SRAM cell has smaller area than conventional bulk 6T SRAM cells and 4T SRAM cells.The speed and power dissipation of the SRAM cell are simulated and discussed.The SRAM cell can operate with a 0.5V supply voltage.

Key words: SRAM cellSOI4T-SRAM32nm technology node

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    Received: 18 August 2015 Revised: 10 June 2008 Online: Published: 01 October 2008

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      Zhang Wancheng, Wu Nanjian. A Novel 4T nMOS-Only SRAM Cell in 32nm Technology Node[J]. Journal of Semiconductors, 2008, 29(10): 1917-1921. ****Zhang W C, Wu N J. A Novel 4T nMOS-Only SRAM Cell in 32nm Technology Node[J]. J. Semicond., 2008, 29(10): 1917.
      Citation:
      Zhang Wancheng, Wu Nanjian. A Novel 4T nMOS-Only SRAM Cell in 32nm Technology Node[J]. Journal of Semiconductors, 2008, 29(10): 1917-1921. ****
      Zhang W C, Wu N J. A Novel 4T nMOS-Only SRAM Cell in 32nm Technology Node[J]. J. Semicond., 2008, 29(10): 1917.

      A Novel 4T nMOS-Only SRAM Cell in 32nm Technology Node

      • Received Date: 2015-08-18
      • Accepted Date: 2008-05-06
      • Revised Date: 2008-06-10
      • Published Date: 2008-11-11

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