Degradation of nMOS and pMOSFETs with Ultrathin Gate Oxide Under DT Stress

Hu Shigang; Hao Yue; Ma Xiaohua; Cao Yanrong; Chen Chi; Wu Xiaofeng

J. Semicond. > 2008, Volume 29 > Issue 11 > 2136-2142

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Degradation of nMOS and pMOSFETs with Ultrathin Gate Oxide Under DT Stress

Hu Shigang, Hao Yue, Ma Xiaohua, Cao Yanrong, Chen Chi and Wu Xiaofeng

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Abstract: The degradation of device parameters and the degradation of the stress induced leakage current (SILC) of thin tunnel gate oxide under constant direct-tunneling voltage stress are studied using nMOS and pMOSFETs with 1.4nm gate oxides.Experimental results show that there is a linear correlation between the degradation of the SILC and the degradation of Vth in MOSFETs during different direct-tunneling (DT) stresses.A model of tunneling assisted by interface traps and oxide trapped positive charges is developed to explain the origin of SILC during DT stress.

Key words: threshold voltage, interface traps, direct tunneling, SILC

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Hu Shigang, Hao Yue, Ma Xiaohua, Cao Yanrong, Chen Chi, Wu Xiaofeng. Degradation of nMOS and pMOSFETs with Ultrathin Gate Oxide Under DT Stress[J]. Journal of Semiconductors, 2008, 29(11): 2136-2142.

Hu S G, Hao Y, Ma X H, Cao Y R, Chen C, Wu X F. Degradation of nMOS and pMOSFETs with Ultrathin Gate Oxide Under DT Stress[J]. J. Semicond., 2008, 29(11): 2136.

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Received: 18 August 2015 Revised: 23 June 2008 Online: Published: 01 November 2008

The degradation of device parameters and the degradation of the stress induced leakage current (SILC) of thin tunnel gate oxide under constant direct-tunneling voltage stress are studied using nMOS and pMOSFETs with 1.4nm gate oxides.Experimental results show that there is a linear correlation between the degradation of the SILC and the degradation of Vth in MOSFETs during different direct-tunneling (DT) stresses.A model of tunneling assisted by interface traps and oxide trapped positive charges is developed to explain the origin of SILC during DT stress.

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