Chin. J. Semicond. > 2007, Volume 28 > Issue 4 > 576-581

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RTS Noise in Ultra-Thin Oxide nMOSFET under High Gate Bias

Bao Li, Zhuang Yiqi, Bao Junlin and Li Weihua

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Abstract: The timing characteristics of RTS in SMIC 90nm CMOS nMOS devices with a 1.4nm gate oxide are measured and analyzed.It is proposed that tunneling through the gate dielectric of electrons in the conduction band is responsible for RTS noise,and a detailed description of the mechanics of the RTS noise under high gate bias is presented.Also,based on the research from IMEC and TSMC,a physical model of the timing characteristics of the RTS noise versus gate bias is constructed,and the consistency of the experiment and the simulation shows the effectiveness of this model.The research in this paper provides new measures for dynamic characterization of border traps and the reliability of deep sub-micron MOS devices.

Key words: RTSdeep sub-micronborder trapsMOS device

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    Received: 18 August 2015 Revised: 05 December 2006 Online: Published: 01 April 2007

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      Bao Li, Zhuang Yiqi, Bao Junlin, Li Weihua. RTS Noise in Ultra-Thin Oxide nMOSFET under High Gate Bias[J]. Journal of Semiconductors, 2007, 28(4): 576-581. ****Bao L, Zhuang Y Q, Bao J L, Li W H. RTS Noise in Ultra-Thin Oxide nMOSFET under High Gate Bias[J]. Chin. J. Semicond., 2007, 28(4): 576.
      Citation:
      Bao Li, Zhuang Yiqi, Bao Junlin, Li Weihua. RTS Noise in Ultra-Thin Oxide nMOSFET under High Gate Bias[J]. Journal of Semiconductors, 2007, 28(4): 576-581. ****
      Bao L, Zhuang Y Q, Bao J L, Li W H. RTS Noise in Ultra-Thin Oxide nMOSFET under High Gate Bias[J]. Chin. J. Semicond., 2007, 28(4): 576.

      RTS Noise in Ultra-Thin Oxide nMOSFET under High Gate Bias

      • Received Date: 2015-08-18
      • Accepted Date: 2006-10-13
      • Revised Date: 2006-12-05
      • Published Date: 2007-04-09

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