| Citation: |
Chen Yingmei, Wang Zhigong, Zhang Li. Fast-Lock Low-Jitter PLL with a Simple Phase-Frequency Detector[J]. Journal of Semiconductors, 2008, 29(1): 88-92.
****
Chen Y M, Wang Z G, Zhang L. Fast-Lock Low-Jitter PLL with a Simple Phase-Frequency Detector[J]. J. Semicond., 2008, 29(1): 88.
|
Fast-Lock Low-Jitter PLL with a Simple Phase-Frequency Detector
-
Abstract
A fast-locking,low-jitter,phase-locked loop (PLL) with a simple phase-frequency detector is proposed.The phase-frequency detector is composed of only two XOR gates.It simultaneously achieves low jitter and short locking time.The voltage-controlled oscillator within the PLL consists of four-stage ring oscillators which are coupled to each other and oscillate with the same frequency and a phase shift of 45° .The PLL is fabricated in 0.18μm CMOS technology.The measured phase noise of the PLL output at 500kHz offset from the 5GHz center frequency is -102.6dBc/Hz.The circuit exhibits a capture range of 280MHz and a low RMS jitter of 2.06ps.The power dissipation excluding the output buffers is only 21.6mW at a 1.8V supply. -
References
-
Proportional views
DownLoad: