Citation: |
Jia Hailong, Ren Tong, Lin Min, Chen Fangxiong, Shi Yin, Dai F F. A Low Power Dissipation Wide-Band CMOS Frequency Synthesizer for a Dual-Band GPS Receiver[J]. Journal of Semiconductors, 2008, 29(10): 1968-1973.
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Jia H L, Ren T, Lin M, Chen F X, Shi Y, Dai F F. A Low Power Dissipation Wide-Band CMOS Frequency Synthesizer for a Dual-Band GPS Receiver[J]. J. Semicond., 2008, 29(10): 1968.
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A Low Power Dissipation Wide-Band CMOS Frequency Synthesizer for a Dual-Band GPS Receiver
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Abstract
This paper presents a wide tuning range CMOS frequency synthesizer for a dual-band GPS receiver,which has been fabricated in a standard 0.18μm RF CMOS process.With a high Q on-chip inductor,the wide-band VCO shows a tuning range from 2 to 3.6GHz to cover 2.45 and 3.14GHz in case of process corner or temperature variation,with a current consumption varying accordingly from 0.8 to 0.4mA,from a 1.8V supply voltage.Measurement results show that the whole frequency synthesizer consumes very low power of 5.6mW working at L1 band with in-band phase noise less than -82dBc/Hz and out-of-band phase noise about -112dBc/Hz at 1MHz offset from a 3.142GHz carrier.The performance of the frequency synthesizer meets the requirements of GPS applications very well. -
References
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