Abstract: A novel method to characterize CMOS process fluctuations in subthreshold current mirrors (SCM) is reported.The proposed model is succinct in methodology and calculation complexity compared with previous statistical models.However,it provides favorable estimations of CMOS process fluctuations on the SCM circuit,which makes it promising for engineering applications.The model statistically Abstracts physical parameters,which depend on the IC process,into random variables with certain mean values and standard deviations,while aggregating all the random impacts into a discrete martingale.The correctness of the proposed method is experimentally verified on an SCM circuit implemented in an SMIC 0.18μm CMOS 1P6M mixed signal process with a conversion factor of 100 in an input range from 100pA to 1μA.The proposed theory successfully predicts ~10% of die-to-die fluctuation measured in the experiment,and also suggests the ~1mV of threshold voltage standard deviation over a single die,which meets the process parameters suggested by the design kit from the foundry.The deviations between calculated probabilities and measured data are less than 8%.Meanwhile,pertinent suggestions concerning high fluctuation tolerance subthreshold analog circuit design are also made and discussed.

Key words: CMOS process fluctuations, subthreshold current mirror, random variable, probability, discrete martingale