Chin. J. Semicond. > 2007, Volume 28 > Issue 4 > 614-618

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Design of a High-Speed Low-Power 9-Port Register File

Cong Gaojian and Qi Jiayue

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Abstract: A 1-write-port 8-read-port 32×32-bit register file has been designed in 1.8V 0.18μm CMOS technology. Low-swing bit-lines are used for both read and write operations. Together with the use of novel memory cells, high speed sensor amplifiers, self-reset address decoders, SCL circuits, clock gating, and delicate time control circuits, it has achieved both high speed and low power. Post-layout simulations in 1.8V with HSPICE indicate a write time of 1.7ns and a read time of 1.32ns. The power dissipation is 70mW for all 9 ports at 500MHz.

Key words: high speedlow powermulti-portSRAMregister file

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    Received: 18 August 2015 Revised: 21 October 2006 Online: Published: 01 April 2007

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      Cong Gaojian, Qi Jiayue. Design of a High-Speed Low-Power 9-Port Register File[J]. Journal of Semiconductors, 2007, 28(4): 614-618. ****Cong G J, Qi J Y. Design of a High-Speed Low-Power 9-Port Register File[J]. Chin. J. Semicond., 2007, 28(4): 614.
      Citation:
      Cong Gaojian, Qi Jiayue. Design of a High-Speed Low-Power 9-Port Register File[J]. Journal of Semiconductors, 2007, 28(4): 614-618. ****
      Cong G J, Qi J Y. Design of a High-Speed Low-Power 9-Port Register File[J]. Chin. J. Semicond., 2007, 28(4): 614.

      Design of a High-Speed Low-Power 9-Port Register File

      • Received Date: 2015-08-18
      • Accepted Date: 2006-09-14
      • Revised Date: 2006-10-21
      • Published Date: 2007-04-09

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