Two-dimensional pixel image lag simulation and optimization in a 4-T CMOS image sensor

Yu Junting; Li Binqiao; Yu Pingping; Xu Jiangtao; Mou Cun

doi:10.1088/1674-4926/31/9/094011

J. Semicond. > 2010, Volume 31 > Issue 9 > 094011

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Two-dimensional pixel image lag simulation and optimization in a 4-T CMOS image sensor

Yu Junting, Li Binqiao, Yu Pingping, Xu Jiangtao and Mou Cun

+ Author Affiliations

DOI: 10.1088/1674-4926/31/9/094011

Abstract: Pixel image lag in a 4-T CMOS image sensor is analyzed and simulated in a two-dimensional model. Strategies of reducing image lag are discussed from transfer gate channel threshold voltage doping adjustment, PPD N-type doping dose/implant tilt adjustment and transfer gate operation voltage adjustment for signal electron transfer. With the computer analysis tool ISE-TCAD, simulation results show that minimum image lag can be obtained at a pinned photodiode n-type doping dose of 7.0 × 10¹² cm^–2, an implant tilt of –2^o, a transfer gate channel doping dose of 3.0 × 10¹² cm^-2 and an operation voltage of 3.4 V. The conclusions of this theoretical analysis can be a guideline for pixel design to improve the performance of 4-T CMOS image sensors.

Key words: image lag, two-dimensional simulation, doping dose, implant tilt, CMOS image sensor

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Yu Junting, Li Binqiao, Yu Pingping, Xu Jiangtao, Mou Cun. Two-dimensional pixel image lag simulation and optimization in a 4-T CMOS image sensor[J]. Journal of Semiconductors, 2010, 31(9): 094011. doi: 10.1088/1674-4926/31/9/094011

Yu J T, Li B Q, Yu P P, Xu J T, Mou C. Two-dimensional pixel image lag simulation and optimization in a 4-T CMOS image sensor[J]. J. Semicond., 2010, 31(9): 094011. doi: 10.1088/1674-4926/31/9/094011.

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Received: 18 August 2015 Revised: Online: Published: 01 September 2010

Pixel image lag in a 4-T CMOS image sensor is analyzed and simulated in a two-dimensional model. Strategies of reducing image lag are discussed from transfer gate channel threshold voltage doping adjustment, PPD N-type doping dose/implant tilt adjustment and transfer gate operation voltage adjustment for signal electron transfer. With the computer analysis tool ISE-TCAD, simulation results show that minimum image lag can be obtained at a pinned photodiode n-type doping dose of 7.0 × 10¹² cm^–2, an implant tilt of –2^o, a transfer gate channel doping dose of 3.0 × 10¹² cm^-2 and an operation voltage of 3.4 V. The conclusions of this theoretical analysis can be a guideline for pixel design to improve the performance of 4-T CMOS image sensors.

Two-dimensional pixel image lag simulation and optimization in a 4-T CMOS image sensor

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