Chin. J. Semicond. > 2005, Volume 26 > Issue 8 > 1656-1661
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可缩放的开路通路地屏蔽电感在片测试结构去嵌入方法

菅洪彦 , 唐珏 , 唐长文 , 何捷 and 闵昊

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Key words: 片上电感, 按比例缩放, 开路通路去嵌入, 在片测试

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    Received: 18 August 2015 Revised: Online: Published: 01 August 2005

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      Article Navigation >  Journal of Semiconductors  > 2005  >  26(8): 1656-1661
      菅洪彦, 唐珏, 唐长文, 何捷, 闵昊. 可缩放的开路通路地屏蔽电感在片测试结构去嵌入方法[J]. 半导体学报(英文版), 2005, 26(8): 1656-1661.
      Citation:
      菅洪彦, 唐珏, 唐长文, 何捷, 闵昊. 可缩放的开路通路地屏蔽电感在片测试结构去嵌入方法[J]. 半导体学报(英文版), 2005, 26(8): 1656-1661.
      shu

      • Received Date: 2015-08-18

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