| Citation: |
Sun Yehui, Jiang Lixin, Qin Shicai. A Low Voltage Low Power CMOS 5Gb/s Transceiver[J]. Journal of Semiconductors, 2007, 28(8): 1283-1288.
****
Sun Y H, Jiang L X, Qin S C. A Low Voltage Low Power CMOS 5Gb/s Transceiver[J]. Chin. J. Semicond., 2007, 28(8): 1283.
|
A Low Voltage Low Power CMOS 5Gb/s Transceiver
-
Abstract
A low voltage and low power SerDes transceiver implemented in 0.13μm CMOS is described.The power supply voltage is 1V,and the operating frequency range is from 2.5 to 5GHz.The transmitter includes a 20∶1 serializer and a transmission driver,the latter of which uses pre-emphasis architecture for channel compensation.The receiver employs two 1∶20 deserializer,an input signal pre-amplifier,and a clock and data recovery circuit.The pre-amplifier employs a novel architecture,consisting of a feed-forward equalizer to cancel ISI.The measured transceiver power consumption is 127mW/channel.The RMS jitter of the transmitter output is 4ps.Test results indicate the receiver BER is less than 1e-12 when the input signal amplitude is 150mV differential peak to peak and the eye closure is 0.5UI.-
Keywords:
- low voltage,
- low power,
- transceiver,
- equalization
-
References
-
Proportional views
DownLoad: