| Citation: |
Yang Bin, Yin Xiumei, Yang Huazhong. A High-Speed High-Resolution Sample-and-Hold Circuit[J]. Journal of Semiconductors, 2007, 28(10): 1642-1646.
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Yang B, Yin X M, Yang H Z. A High-Speed High-Resolution Sample-and-Hold Circuit[J]. Chin. J. Semicond., 2007, 28(10): 1642.
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A High-Speed High-Resolution Sample-and-Hold Circuit
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Abstract
A high performance CMOS sample and hold (S/H) circuit for use in the front end of a 12bit 100MS/s ADC is presented.It achieves a 108dB spurious-free dynamic range and 77dB signal-to-noise ratio over the Nyquist band at a 100MHz sampling frequency with a 3V power supply.An analysis model for the S/H circuit is built to capture the switching effect.The impact of the switches’ arrangement is also addressed.The leakage in a conventional bootstrapped switch is analyzed and some improvements are made,enhancing the linearity significantly. -
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