A CMOS Low Power Fully Differential Sigma-Delta Frequency Synthesizer for 2Mb/s GMSK Modulation

Zhang Li; Chi Baoyong; Yao Jinke; Wang Zhihua; Chen Hongyi

Chin. J. Semicond. > 2006, Volume 27 > Issue 12 > 2106-2111

PAPERS

A CMOS Low Power Fully Differential Sigma-Delta Frequency Synthesizer for 2Mb/s GMSK Modulation

Zhang Li, Chi Baoyong, Yao Jinke, Wang Zhihua and Chen Hongyi

+ Author Affiliations

Abstract: A CMOS fully-differential 2.4GHz ∑-△ frequency synthesizer for Gaussian minimum shift keying(GMSK)modulation is presented.A pre-compensation fractional-N phase-locked loop(PLL)is adopted in the modulator.The transfer function of the type-II third-order phase-locked loop is deduced,and the important parameters that affect the loop transfer function are pointed out.Methods to calibrate the important loop parameters are introduced.A differential tuned LC-VCO and a fully-differential charge pump are adopted in the PLL design.The designed circuits are simulated in a 0.18μm 1P6M CMOS process.The power consumption of the PLL is only about 11mW with the low power consideration in building blocks design,and the data rate of the modulator can reach 2Mb/s

Key words: CMOS, fractional-N, Gaussian minimum shift keying, phase-locked loop, sigma-delta

1	Low power fast settling multi-standard current reusing CMOS fractional-N frequency synthesizer Lou Wenfeng, Feng Peng, Wang Haiyong, Wu Nanjian Journal of Semiconductors, 2012, 33(4): 045004. doi: 10.1088/1674-4926/33/4/045004
2	A highly linear fully integrated CMOS power amplifier with an analog predistortion technique Jin Boshi, Li Lewei, Wu Qun, Yang Guohui, Zhang Kuang, et al. Journal of Semiconductors, 2011, 32(5): 054006. doi: 10.1088/1674-4926/32/5/054006
3	High performance QVCO design with series coupling in CMOS technology Cai Li, Huang Lu, Ying Yutong, Fu Zhongqian, Wang Weidong, et al. Journal of Semiconductors, 2011, 32(11): 115004. doi: 10.1088/1674-4926/32/11/115004
4	A 0.5–1.7 GHz low phase noise ring-oscillator-based PLL for mixed-signal SoCs Jiao Yishu, Zhou Yumei, Jiang Jianhua, Wu Bin Journal of Semiconductors, 2010, 31(9): 095002. doi: 10.1088/1674-4926/31/9/095002
5	Sigma–delta modulator modeling analysis and design Ge Binjie, Wang Xin'an, Zhang Xing, Feng Xiaoxing, Wang Qingqin, et al. Journal of Semiconductors, 2010, 31(9): 095003. doi: 10.1088/1674-4926/31/9/095003
6	A novel 2.95–3.65 GHz CMOS LC-VCO using tuning curve compensation Xiao Shimao, Ma Chengyan, Ye Tianchun Journal of Semiconductors, 2009, 30(10): 105001. doi: 10.1088/1674-4926/30/10/105001
7	A Σ-Δ Fractional-N PLL Frequency Synthesizer with AFC for SRD Applications Zhang Huajiang, Hu Kangmin, Hong Zhiliang Journal of Semiconductors, 2008, 29(7): 1298-1304.
8	Transient Characteristic Analysis of a Double-Gate Dual-Strained-Channel SOI CMOS Sun Liwei, Gao Yong, Yang Yuan, Liu Jing Journal of Semiconductors, 2008, 29(8): 1566-1569.
9	Analysis and Modeling of Broadband CMOS Monolithic Balun up to Millimeter-Wave Frequencies Xia Jun, Wang Zhigong, Wu Xiushan, Li Wei Journal of Semiconductors, 2008, 29(3): 467-472.
10	A High Speed,12-Channel Parallel,Monolithic IntegratedCMOS OEIC Receiver Zhu Haobo, Mao Luhong, Yu Changliang, Chen Hongda, Tang Jun, et al. Chinese Journal of Semiconductors , 2007, 28(9): 1341-1345.
11	Design of a Wideband CMOS Variable Gain Amplifier Guo Feng, Li Zhiqun, Chen Dongdong, Li Haisong, Wang Zhigong, et al. Chinese Journal of Semiconductors , 2007, 28(12): 1967-1971.
12	Concept and Simulation of a Novel Pre-Equalized CMOS Optoelectronic Integrated Receiver Yu Changliang, Mao Luhong, Zhu Haobo, Song Ruiliang, Chen Mingyi, et al. Chinese Journal of Semiconductors , 2007, 28(6): 951-957.
13	Study on Si-SiGe Three-Dimensional CMOS Integrated Circuits Hu Huiyong, Zhang Heming, Jia Xinzhang, Dai Xianying, Xuan Rongxi, et al. Chinese Journal of Semiconductors , 2007, 28(5): 681-685.
14	Low-Power CMOS IC for Function Electrical Stimulation of Nerves Li Wenyuan, Wang Zhigong, 张震宇 Chinese Journal of Semiconductors , 2007, 28(3): 393-397.
15	A Model of the Temperature Dependence of the Fall Time ofa TF SOI CMOS Inverter with EM NMOST and AMPMOST Assemblies at 27～300℃ Zhang Haipeng, Wei Tongli, Feng Yaolan, Wang Qin, Zhang Zhengfan, et al. Chinese Journal of Semiconductors , 2006, 27(S1): 36-39.
16	Characterization and Modeling of Finite-Ground Coplanar Waveguides in 0.13μm CMOS Chen Xu, Wang Zhigong Chinese Journal of Semiconductors , 2006, 27(6): 982-987.
17	An Integrated Four Quadrant CMOS Analog Multiplier Huo Mingxue, Tan Xiaoyun, Liu Xiaowei, Wang Yonggang, Ren Lianfeng, et al. Chinese Journal of Semiconductors , 2006, 27(S1): 335-339.
18	A Novel Method to Compensate the Sigma-Delta Shaped Noise for Wide Band Fractional-N Frequency Synthesizers Shi Hao, Liu Junhua, Zhang Guoyan, Liao Huailin, Huang Ru, et al. Chinese Journal of Semiconductors , 2006, 27(4): 646-652.
19	A Novel Offset-Cancellation Technique for Low Voltage CMOS Differential Amplifiers Han Shuguang, Chi Baoyong, Wang Zhihua Chinese Journal of Semiconductors , 2006, 27(5): 778-782.
20	A Fractional-N CMOS DPLL with Self-Calibration Liu Sujuan, Yang Weiming, Chen Jianxin, Cai Liming, Xu Dongsheng, et al. Chinese Journal of Semiconductors , 2005, 26(11): 2085-2091.

Search

GET CITATION

shu

Export: BibTex EndNote

Article Metrics

Article views: 3755 Times PDF downloads: 1319 Times Cited by: 0 Times

History

Received: 18 August 2015 Revised: 26 July 2006 Online: Published: 01 December 2006

A CMOS fully-differential 2.4GHz ∑-△ frequency synthesizer for Gaussian minimum shift keying(GMSK)modulation is presented.A pre-compensation fractional-N phase-locked loop(PLL)is adopted in the modulator.The transfer function of the type-II third-order phase-locked loop is deduced,and the important parameters that affect the loop transfer function are pointed out.Methods to calibrate the important loop parameters are introduced.A differential tuned LC-VCO and a fully-differential charge pump are adopted in the PLL design.The designed circuits are simulated in a 0.18μm 1P6M CMOS process.The power consumption of the PLL is only about 11mW with the low power consideration in building blocks design,and the data rate of the modulator can reach 2Mb/s

A CMOS Low Power Fully Differential Sigma-Delta Frequency Synthesizer for 2Mb/s GMSK Modulation

Search

GET CITATION

Share:

Article Metrics

History

Catalog

Email This Article

A CMOS Low Power Fully Differential Sigma-Delta Frequency Synthesizer for 2Mb/s GMSK Modulation

Abstract

References

Proportional views

Catalog

A CMOS Low Power Fully Differential Sigma-Delta Frequency Synthesizer for 2Mb/s GMSK Modulation

Search

GET CITATION

Share:

Article Metrics

History

Catalog

Email This Article

A CMOS Low Power Fully Differential Sigma-Delta Frequency Synthesizer for 2Mb/s GMSK Modulation

Abstract

References

Proportional views

Catalog

Export File

Citation

Format

Content