Chin. J. Semicond. > 2003, Volume 24 > Issue 2 > 203-208
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改进结构的64位CMOS并行加法器设计与实现

孙旭光 , 毛志刚 and 来逢昌

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Key words: 二进制并行加法器, 时钟延迟多米诺逻辑, 动态复合门

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    Received: 20 August 2015 Revised: Online: Published: 01 February 2003

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      Article Navigation >  Journal of Semiconductors  > 2003  >  24(2): 203-208
      孙旭光, 毛志刚, 来逢昌. 改进结构的64位CMOS并行加法器设计与实现[J]. 半导体学报(英文版), 2003, 24(2): 203-208.
      Citation:
      孙旭光, 毛志刚, 来逢昌. 改进结构的64位CMOS并行加法器设计与实现[J]. 半导体学报(英文版), 2003, 24(2): 203-208.
      shu

      • Received Date: 2015-08-20

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