
PAPERS
Abstract: To investigate the influence of electrical overstress (EOS) on the reliability of power MOSFETs, failure analysis is employed to assess the reliability of devices, including defects related to solder void, gate openings, and die cracks.After using finite element analysis, a circuit simulation, and a reliability accelerated test, the root cause of EOS is confirmed.EOS resistance of the devices after optimizing the die attach temperature-time curve is compared with that of the devices before the optimization using unclamped inductive loading test.The volume of solder void is observably decreased and EOS resistance is improved after optimization.
Key words: EOS, failure analysis, MOSFET, die attach, process optimization
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A Forecast Technique for Radiation-Resistant Capability on MOSFETs Peng Shaoquan, Du Lei, Zhuang Yiqi, Bao Junlin, Liu Jiang, et al. Journal of Semiconductors, 2008, 29(7): 1360-1364. |
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Characteristics of Nanometer MOSFETs with Mechanical Strain in the Channel Wu Tao, Du Gang, Liu Xiaoyan, Kang Jinfeng, Han Ruqi, et al. Chinese Journal of Semiconductors , 2006, 27(S1): 415-418. |
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Device Simulation of Nano-Scale MOSFETs Based on Bandstructure Calculation Yu Zhiping, Tian Lilin Chinese Journal of Semiconductors , 2006, 27(S1): 248-251. |
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Refinement of an Analytical Approximation of the Surface Potential in MOSFETs Lu Jingxue, Huang Fengyi, Wang Zhigong, Wu Wengang Chinese Journal of Semiconductors , 2006, 27(7): 1155-1158. |
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Unified MOSFET Short Channel Factor Using Variational Method Chinese Journal of Semiconductors , 2000, 21(5): 431-436. |
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Received: 18 August 2015 Revised: 11 September 2007 Online: Published: 01 February 2008
Citation: |
Wu Dinghe, Shen Meng, Shao Xuefeng, Yu Hongkun. EOS Failure Analysis and Die Attach Optimization[J]. Journal of Semiconductors, 2008, 29(2): 381-386.
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Wu D H, Shen M, Shao X F, Yu H K. EOS Failure Analysis and Die Attach Optimization[J]. J. Semicond., 2008, 29(2): 381.
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