High performance 20 nm GaSb/InAs junctionless tunnel field effect transistor for low power supply

  • Department of Electrical Engineering, Indian Institute of Technology Kanpur, Kanpur 208016, India

Key words: band tunneling (BTBT)tunnel field effect transistor (TFET)junctionless tunnel field effect transistor (JLTFET)ION/IOFF ratiolow powerdigital switching

Abstract: We present a GaSb/InAs junctionless tunnel FET and investigate its static device characteristics. The proposed structure presents tremendous performance at a very low supply voltage of 0.4 V. The key idea is to the present device architecture, which can be exploited as a digital switching device for sub 20 nm technology. Numerical simulations resulted in an IOFF of ~8 × 10-17 A/μm, ION of ~ 9 μA/μm, ION/IOFF of ~1 × 1011, subthreshold slope of 9.33 mV/dec and DIBL of ~ 87 mV/V for GaSb/InAs JLTFET at a temperature of 300 K, gate length of 20 nm, HfO2 gate dielectric thickness of 2 nm, film thickness of 10 nm, low-k spacer thickness of 10 nm and VDD of 0.4 V.

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1.   Introduction
  • The presence of two doping junctions in a MOSFET leads to size constraint and so its future[1, 2, 3, 4, 5, 6, 7, 8, 9]. Now concentration is shifting towards a sustainable solution of junction constraint with better gate control[10, 11, 12, 13, 14, 15, 16]. Structures like having the gate all around, vertical poly-Si nanowire and the omega gate were fabricated[10, 14, 17, 18, 19, 20]. However, they either suffered from fabrication related issues beyond sub 30 nm technology or yielded poor performance[12, 18, 20, 21, 22, 23, 24]. Therefore, Lilienfeld's first transistor architecture, which was filed for patent in 1925, has attracted new attention[25]. Recently, a junctionless field effect transistor (JLFET) was successfully fabricated which did not have any metallurgical junction[26, 27, 28, 29]. It drew attention due to its excellent performance[28, 30, 31]. The JLFETs have provided a potential solution to the problem faced in MOSFETs for sub 30 nm technology, as they do not have doping junctions[32]; it has shown itself as a potential candidate by providing good transfer characteristics with size scaling[33]. Major applications of this include memory devices[34]. However, it has huge leakage due to bulk conduction and therefore, power consumption is high in these devices.

    Recently, junctionless tunnel FETs (JLTFET) have become an alternative attractive device due to a low sub threshold slope of less than 60 mV/decade as in conventional MOSFETs at room temperature and subdued leakage current[35, 36, 37, 38]. The lower subthreshold slope than conventional MOSFETs and JLFETs at room temperature overcomes the limitation of these structures and opens new possibilities for future low power switching devices[39, 40]. The JLTFET has been proposed as a solution for the many problems encountered in conventional CMOS technology such as scalability, low SS, and ON-OFF current ratio. JLTFETs also feature high speed due to large drive current and simultaneously highly suppressed leakage[41, 42]. In this paper, we present 2D numerical simulations based results. We have designed and optimized the architecture of the 20 nm GaSb/InAs junctionless tunnel field effect transistor (JLTFET). We have investigated the energy band diagram, and the electron and hole concentration profile in the ON state and OFF states for a GaSb/InAs JLTFET. Also, the lateral electric field and potential pattern of the device is examined in both the states. We have simulated the recombination rate of the GaSb/InAs JLTFET as a function of position in the OFF and ON states. Further, transfer characteristics and transconductance of the proposed structure are simulated for different drain voltages. Additionally, output characteristics, output transconductance, $C_{\rm GD}$, and $C_{\rm GS}$ are explored for our device structure.

2.   Device structure and parameters

    2.1.   Device structure

  • A schematic of the proposed device structure is shown in Figure 1. The GaSb/InAs JLTFET does not have any doping junction because the channel is uniformly n-type doped. Since the device is junctionless therefore, in the OFF state, the device completely depletes due to the work function difference between the gate electrode and channel. However, above the threshold in the ON state, bulk conduction occurs rather than inversion as in MOSFETs due to the applied gate voltage overcoming the work function differences. Moreover, since the GaSb/InAs JLTFET is a tunnelling device along with being junctionless, therefore, the current conduction phenomenon is completely different from inversion mode devices[43, 44, 45, 46, 47]. In JLTFETs, there is band to band tunnelling (BTBT) of electrons from the valence band of the source to the conduction band of the channel and from the valence band of the channel to the conduction band of the drain, while in conventional MOSFETs, there is drift-diffusion of charge carriers[44, 48, 49]. The JLTFET is a quantum mechanical device (QMD) and tunnelling of electrons depends on the barrier widths between the energy bands of the source and channel, and the channel and drain[50, 51]. This barrier width is controlled by the applied gate voltage. The source, gate and drain electrodes with work functions of 5.3, 4.7 and 4.2 eV respectively, along with n$^{+}$ channel create p-type, intrinsic and n-type regions using the charge plasma concept. Therefore, work function engineering causes the device to operate in a junctionless mode and is simultaneously exploited as a charge plasma concept. The electron and hole concentration variation with position at the channel and gate dielectric interface for ON-state and OFF-state is shown in Figure 2. GaSb with a band gap of 0.726 eV in the drain side and InAs with a band gap of 0.354 eV in the source side enhances BTBT between the source and the channel, while it depreciates between the channel and drain in comparison to a homogeneous InAs or GaSb channel. This is later on manifested in our device simulations. An energy band diagram of the GaSb/InAs JLTFET at the channel and gate dielectric interface for ON-state and OFF-state is shown in Figure 3. As indicted in the figure, in the OFF state, very small leakage current flows due to the large barrier width for tunnelling. $I_{\rm OFF}$ is comprised of p-i-n reverse bias current and OFF state tunnelling current. On the contrary, in the ON-state, the gate voltage brings bands down and therefore the barrier width decreases sharply causing a high drive current. Figure 4 illustrates the lateral electric field of GaSb/InAs JLTFET as a function of the position along the x-direction in OFF and ON states. Four peaks, p1-p4, of the field are observed beneath the terminals of the drain, gate and source electrodes. This variation in the lateral electric field can be understood through the concentration profile of carriers in Figure 2. Peaks in the field are observed at doping junctions however, here these junctions are created using the charge plasma concept as the channel is junctionless with uniform doping. The highest peak is observed between the source and channel in both states while the p2 and p3 become weaker in the ON state than in the OFF state due to a variation in the concentration profile. P1 is the second most dominant peak, which is between the drain and channel. It is clear from Figure 2 that the highest charge density is noticed at the source side and so the field p4, while the lowest is at 45 nm i.e. p3 where the interface of GaSb and InAs is located. Figure 5 shows the potential between the drain and source variation with the position for GaSb/InAs JLTFET. From the figure, it is explicit that the voltage is gradually varying from the drain towards the source side with the flat region indicating the region below the gate electrode where no doping junctions are present and the electric field is almost zero, as in Figure 4. In the ON-state, due to the positive gate voltage, potential increases since the electron concentration increases, as in Figure 2. Figure 6 shows the recombination rate variation with position. As shown in the figure, in the OFF-state, the rate of recombination is almost negligible, while in the ON-state, the recombination rate increases due to the lowering of the barrier width between the source and the channel.

    Earlier significant work has been done on GaSb:InAs hetero-structure[52, 53]. Recently, there have been many successful efforts to fabricate the GaSb and InAs interface through the hetero-epitaxial growth of InAs on GaSb[54, 55]. In a similar fashion, GaSb:InAs JLTFET could be fabricated through epitaxial growth, preferably MBE growth, with a vertical interface. Fabrication of this interface can be done using vertical hetero-structuring. It has resulted in the successful fabrication of various devices[52, 53, 54, 55, 56, 57, 58]. For oxide as a gate dielectric, oxygen exposure on III-V surfaces results in `Fermi-level pinning' causing the electrostatic potential inside the semiconductor to be stagnant[44]. Therefore, fabrication of III-V MOSFET structure failed due to the low stability and reliability. Recently, a breakthrough has been achieved using Al$_{2}$O$_{3}$ and HfO$_{2}$ as the dielectric for III-V channels through atomic layer deposition (ALD)[44, 59, 60, 61]. During fabrication through ALD, surface oxides are largely eliminated[60].

    The parameters used for this structure in our simulation are: gate dielectric, HfO$_{2}$ thickness ($T_{\rm OX})$ $=$ 2 nm, $\varepsilon_{\rm dielectric}$ $=$ 29, oxide spacer thickness ($T_{\rm SP})$ $=$ 10 nm, $\varepsilon_{\rm spacer}$ $=$ 3.9, film thickness ($T_{\rm S})$ $=$ 10 nm, gate length ($L$) $=$ 20 nm, source/drain length ($L_{\rm D})$ $=$ 10 nm, gate work function ($\Phi_{\rm G})$ $=$ 4.7 eV, source electrode (Cu), work function ($\Phi_{\rm S})$ $=$ 5.3 eV, drain electrode (Al) work function ($\Phi_{\rm D})$ $=$ 4.2 eV, supply voltage ($V_{\rm DD})$ $=$ 0.4 V, carrier concentration in channel ($n$) $=$ 1.0 $\times$ 10$^{18}$ cm$^{-3}$ and temperature for simulation ($T$) $=$ 300 K.

  • 2.2.   Simulation setup

  • Simulations are done in SILVACO ATLAS 2D V5.15.32 R[64]. The drift-diffusion current transport model and the Lombardi mobility model are used for simulations. A non local band to band tunnelling model is included for studying the effect of tunnelling. As the channel is heavily doped, the band gap narrowing (BGN) model has been added. The OFF-state current of InAs on the insulator is primarily due to the Shockley Read Hall recombination and trap-assisted tunnelling. Therefore, along with the SRH recombination model, Schenk's trap assisted tunnelling (TAT) model is incorporated. Grid points are kept at spacings of 0.1 nm in the $x$-direction and 0.5 nm in the $y$-direction.

3.   Results and discussions
  • The simulated $I_{\rm D}$-$V_{\rm G}$ characteristics for GaSb/InAs JLTFET at different drain voltages are shown in Figure 7. Higher barrier width modulation occurs at a higher gate voltage, which causes higher tunnelling of electrons from the source to the channel, resulting in a larger drain current. The optimized device structure resulted transfer characteristics with $I_{\rm OFF}$ of $\sim $ 8 $\times$ 10$^{-17}$ A/$\mu $m, $I_{\rm ON}$ of $\sim $9 $\mu $A/$\mu $m and $I_{\rm ON}$/$I_{\rm OFF}$ of $\sim $1 $\times$ 10$^{11}$ at a supply voltage of 0.4 V. This figure also portrays the drain induced barrier lowering effect. A subthreshold slope of 9.33 mV/V is calculated for a supply voltage of 0.4 V through the following formula[65]
    ${\rm Average\; subthreshold \;slops \; (SS)}=\frac{V_{\rm t}-V_{\rm ref}}{\lg \dfrac{I_{\rm t}}{I_{\rm ref}}}, $(1)
    where $V_{\rm ref}$ is the voltage at the reference point. We have taken 0.22 V as the reference voltage from where transition starts, as shown in Figure 7 for $V_{\rm DS}$ of 0.4 V. The current at this point i.e. $I_{\rm ref}$ is 8.1 $\times$ 10$^{-17}$ A/$\mu $m. $V_{\rm t}$ is the voltage at the point where the current crosses 10$^{-7}$ A/$\mu $m. $V_{\rm t}$ at this point is 0.305 V for a supply voltage of 0.4 V. The drain induced barrier lowering (DIBL) is calculated from the following formula[66]
    ${\rm DIBL}=\frac{V_{\rm t}/V_{\rm DS=0.4V}-V_{\rm t}/V_{\rm DS=0.01V}} {V_{\rm DS(=0.4 V)}-V_{\rm DS(=0.01 V)}}, $(2)
    where $V_t/V_{\rm DS=0.01V}$ i.e. $V_{\rm t}$ at $V_{\rm DS}$ of 0.01 V is observed to be 0.339 V. GaSb/InAs JLTFET has a DIBL of 87 mV/V. Clearly, it surpasses the International Technology Roadmap for Semiconductors' (ITRS) low standby power (LSTP) standards[67, 68]. The transconductance ($G_{\rm m})$ of the simulated device is shown in Figure 8. The $G_{\rm m}$ is observed of 1.3 $\times$ 10$^{-4}$ S/$\mu $m and 1.8 $\times$ 10$^{-4}$ S/$\mu $m for $V_{\rm DS}$ $=$ 0.01 V and 0.4 V respectively.

    Output characteristics and output transconductance are plotted in Figure 9 with respect to the drain voltage at gate voltages of 0.3 V and 0.4 V. It is explicit from the figure that the GaSb/InAs JLTFET has suppressed short channel effects. Figure 10 portrays the variation of capacitances, $C_{\rm GD}$ and $C_{\rm GS}$, with the gate voltage at $V_{\rm DS}$ $=$ 0.4 V with a small signal voltage of 5 mV and a frequency of 1 MHz. As in conventional MOSFETs, the drain to source capacitance increases with gate voltage at a constant drain voltage, while the gate to source capacitance depreciates with gate voltage; the proposed structure follows the same principle.

4.   Conclusion
  • In summary, we demonstrated a 20 nm GaSb/InAs junctionless tunnel field effect transistor (JLTFET) with a detailed investigation of its characteristics. The small leakage current accomplishes the present demand of highly electrostatic scaled and dense low power VLSI circuits. A small subthreshold at room temperature allows further scaling of the supply voltage ($V_{\rm DD})$. The device exhibits strong drive currents at 0.4 V. The design and optimization of the device architecture is done in such a way that the process budget can be minimized. The suggested structure reduced many fabrication complexities of conventional hetero-structure TFETs. Therefore, it may be a potential candidate for sub 14 nm technology and substantial attention on its process flow may lead towards the same goal.

Figure (10)  Table (2) Reference (68) Relative (20)

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