Novel 700 V high-voltage SOI LDMOS structure with folded drift region

    Corresponding author: Haiou Li,
  • 1. Guangxi Experiment Center of Information Science, Guilin University of Electronic Technology, Guilin 541004, China
  • 2. State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, China

Key words: folded drift regionbreakdown voltageinterdigital oxide layerelectric field modulation

Abstract: A new high-voltage LDMOS with folded drift region (FDR LDMOS) is proposed. The drift region is folded by introducing the interdigital oxide layer in the Si active layer, the result of which is that the effective length of the drift region is increased significantly. The breakdown characteristic has been improved by the shielding effect of the electric field from the holes accumulated in the surface of the device and the buried oxide layer. The numerical results indicate that the breakdown voltage of 700 V is obtained in the proposed device in comparison to 300 V of conventional LDMOS, while maintaining low on-resistance.


1.   Introduction
  • Silicon on insulator (SOI) technology offers tremendous advantages over junction isolation, such as near ideal isolation between devices[1, 2]. The major methods for enhancing the breakdown voltage (BV) of SOI devices are to improve the electric field distribution and increase the drift region length, but the latter leads to high manufacturing costs[3, 4]. To address the issues of the huge size in high-voltage devices, several structures have been proposed[5, 6, 7]: Zhang proposed a variable-$k$ dielectric trench LDMOS, in which a low-$k$ dielectric layer is used to sustain the high voltage and a high-$k$ dielectric layer is used to increase the drift doping concentration[5]; Orouji demonstrated PSOI LDMOS with a step buried oxide layer where the BV is nearly four to five times higher than that of its conventional PSOI counterpart[6]. The structures improving the electric field also include a step buried oxide layer, variable-$k$ buried oxide layer and so on[8, 9].

    The BV has not still obtained satisfying results due to the poor blocking effect of trenches in the surface of the drift region. In this letter, a novel high-voltage LDMOS, characterized by the folded drift region with an improved characteristic of BV and on-resistance, is proposed for the first time. The interdigital oxide trenches are employed to fold the drift region and increase its effective length. The main effects of the doping concentration of the drift region and the parameters of the interdigital trench on the BV are discussed.

2.   Device structure
  • The schematic cross-section of the FDR LDMOS device is illustrated in Figure 1, in which $t_{\rm d}$ and $N_{\rm d}$ are the thickness and doping concentration of the n-type drift region, respectively. $t_{\rm ox}$ is the thickness of the buried oxide layer and $L_{\rm d}$ is the length of the drift region. The height, width and spacing of trenches are $H$, $W$ and $D$, respectively. The p-type substrate doping concentration is $P_{\rm sub}$ and $V_{\rm DS}$ is the voltage applied to the drain. The path sustaining the lateral breakdown voltage is demonstrated by a dashed line; the potential path will increase further with the decrease of the $W$ and $D$. The interdigital oxide trenches in the drift region can be fabricated through the processes in Figure 1(b): trenches etching in silicon wafer $\to$ oxide $\to$ silicon bonding $\to$ trenches etching in SOI.

3.   Results and discussion
  • Numerical simulations were performed by solving Poisson and drift/diffusion equations plus SHR (Shockley-Hall-Read) and Auger generation/recombination and impact ionization processes. The models used in Silvaco include carrier velocity saturation, carrier-carrier scattering at high doping and the dependence of mobility on the temperature and transverse electric field.

    The equipotential contours at breakdown for both devices are given in Figures 2(a) and 2(b). The equipotential contours of the FRD LDMOS are almost uniform; however, the electric field of the conventional SOI LDMOS is mainly concentrated on the ends of the drift region, which results in the degeneration of BV.

    Figure 2(c) gives the distribution of holes along the top surface of the FDR device ($y$ $=$ 0 $\mu$m) and the surface of the buried oxide layer ($y=$ 10 $\mu$m) at $V_{\rm DS}$ $=$ BV. The holes concentration on the buried oxide layer is about 10$^{18}$ cm$^{-3}$ and increases from the source to drain, which not only enhances the electric field in the buried oxide layer, but also modulates the electric field in the drift region; this phenomenon is also observed in Reference [10]. The concentration of holes on the top surface of the device is around 10$^{16}$ cm$^{-3}$ and is almost the same along the device, which can also strengthen the electric field in the oxide layer and increase the lateral BV. The shielding effect of the electric field from the holes leads to the enhancement of the lateral and vertical BVs, and the holes concentration in a trench under the drain increases with an augment of $V_{\rm DS}$. The length of the drift region is lengthened dramatically through folding the drift region by interdigital oxide trenches, which leads to a BV of 700 V in FDR LDMOS. On the contrary, the BV of conventional LDMOS is limited to 300 V due to the U-type distribution of the electric field at the surface in Figure 2(d).

    The BVs as a function of $N_{\rm d}$ with different $D$ and $W$ are shown in Figure 3. With the decrease of $D$ and $W$, the effective length of the drift region increases further and the breakdown characteristic is strengthened. It is clear in Figure 3(a) that the maximal BV increases with a decrease of $D$ and the BV has an optimum. The optimal $N_{\rm d}$ increases with the rise of $D$. The maximum BV and optimal $N_{\rm d}$ decline with a decrease of $W$ in Figure 3(b). For a higher $N_{\rm d}$, the drift region cannot be depleted fully when $N_{\rm d}$ exceeds a certain value and BV declines rapidly. In general, the lower the $W$ and $D$ are, the higher the BV.

    The dependences of BV on $L_{1}$ and $L_{\rm d}$ are illustrated in Figure 4. As seen in Figure 4(a), $N_{\rm d}$ has an optimum when the RESURF (reduced surface field) condition is satisfied. The greater the $L_{1}$ is, the shorter the drift region is and the less the voltage is sustained by the depletion region, thus the maximum BV decreases. The shielding of the electric field from the interdigital oxide trench in the drift region weakens the charge share effect of the drift region, thus the optimum $N_{\rm d}$ increases with the decrease of $L_{1}$. The longer the drift region length is, the higher the BV will be, and BV would also saturate due to the saturation of the vertical BV. This phenomenon is shown in Figure 4(b), where the saturated BV increases with the decrease of $t_{\rm d}$.

    Figure 5 shows the dependences of BV on $t_{\rm ox}$ and $t_{\rm d}$. In Figure 5(a), the optimum $N_{\rm d}$ of the FDR LDMOS is much higher than that of the conventional LDMOS owing to the fact that the n-type charges are very small for introduction of the interdigital oxide trench, which causes the on-resistance of the FDR device to be high, while the BV reaches to 700 V of the FDR device from 300 V of a conventional device. With the increase of $t_{\rm ox}$, the BV rises thanks to the augment of the vertical BV. In Figure 5(b), the BV is enhanced further with the increase of $t_{\rm d}$. When $t_{\rm d}$ is smaller, the BV increases faster and gradually reaches a saturated value.

    The on-state performances of FDR LDMOS are shown in Figure 6. Figures 6(a) and 6(b) give the current and potential distribution, the current lines are mainly distributed in the middle part of the silicon active layer ($V_{\rm GS}$ $=$ 10 V), and most equipotential lines are located in the interdigital oxide trenches; structure parameters are the same as those in Figure 6(c). The height of interdigital oxide trenches near the drain should be increased but others may be decreased in order to improve the tradeoff between BV and on-resistance. Figure 6(c) is the output characteristic curve, that is characterized with a linearization region and a saturation region, which is similar to conventional power LDMOS. When $V_{\rm GS}$ is above 7 V, the impact of the channel resistance is very small, thus the output curves are very close. The influence of $N_{\rm d}$ on BV and on-resistance is shown in Figure 6(d), the on-resistance of the FDR LDMOS is larger than that of a conventional LDMOS due to the fact that the conduction path is lengthened and the amount of carrier is declined, but its BV and the performance ratio of BV/on-resistance are improved greatly. In the FDR device, though the effective length of the drift region is lengthened, the bulk electric field must be improved further using electric field optimization technology in order to increase $N_{\rm d}$ and decrease on-resistance, such as RESURF, superjunction, field plate and so on.

4.   Conclusion
  • In summary, we have presented a novel high-voltage LDMOS with a folded drift region. The lateral effective length of the drift region is increased by interdigital oxide trenches and the breakdown characteristic is enhanced. A large number of holes are accumulated in the top and bottom corners of the interdigital oxide trench, so the electric field in the oxide trench and buried oxide layer is increased but that in the silicon layer is declined. The BV is improved by the shielding effect of the electric field from the holes. The BV will be strengthened further with the decrease of the distance and width of oxide layer trenches. The simulation results have demonstrated a remarkable improvement of the trade-off between the BV and on-resistance compared to the conventional LDMOS.

Figure (6)  Reference (10) Relative (20)

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