A transmission line-type electrical model for tapered TSV considering MOS effect and frequency-dependent behavior

    Corresponding author: Guangbao Shan, 18092060235@189.cn
  • Department of Postgraduates, Xian Microelectronics Technology Research Institute, Xi'an 710065, China

Key words: 3D ICTSVTSV electrical modelMOS effecttransmission line

Abstract: The analytical model of voltage-controlled MOS capacitance of tapered through silicon via (TSV) is derived. To capture the frequency-dependent behavior of tapered TSV, the conventional analytical equations of RLCG for two-wire transmission lines are revised. With the adoption of MOS capacitance model and the revised RLCG analytical equations, a transmission line-type electrical model for tapered TSV is proposed finally. All the proposed models are validated by simulation tools, and a good correlation is obtained between the proposed models and simulations up to 100 GHz. With the proposed model, both the semiconductor phenomenon and frequency-dependent behavior of tapered TSV can be fully captured at high frequency, and the performance of tapered TSV can be evaluated accurately and conveniently prior to 3D IC design.

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1.   Introduction
  • Three-dimensional ICs based on through silicon via (TSV) is a promising solution to overcome the bottlenecks of conventional 2D ICs. With the adoption of TSVs among the stacked dies, the electrical signal can propagate vertical direction with greatly reduced interconnection length, which results in lower latency, lower power consumption, more routing resources and higher bandwidth[1]. As a core element in 3D IC, TSV has a special multilayered structure whose parasitic effects are more complex than the conventional interconnect. Especially at high frequency, the signal loss and other signal integrity problems induced by these parasitic effects have a great influence on the performance of a 3D system. Therefore, it is essential to understand the high frequency electrical properties of TSV accurately and efficiently for subsequent design optimization.

    In order to study the high frequency electrical properties of TSV, it is desirable to have a high frequency electrical model. Currently, there are three primary types of TSV profiles in the industry, namely, cylindrical, tapered, and reentrant[2]. Many works have been done to characterize the parasitic of TSVs with different shapes. In Reference [3], an equivalent circuit model of cylindrical TSV has been proposed and is valid up to 20 GHz. However, the values of RLCG in the equivalent circuit are extracted from cylindrical TSV scattering matrix measurement. In References [4, 5, 6], the scalable electrical models for cylindrical TSV have been proposed, and all the values of RLCG were extracted from analytical equations. Although the above works make a lot of contributions to the electrical model of cylindrical TSV, the real shape of TSV is tapered in current industry. To facilitate the subsequent deposition process after etching, the sidewall of TSV is generally etched with a slope angle. Hence, it is necessary to establish a high frequency electrical model for tapered TSV. Reference [7] gives the analytical expression for the resistance and inductance of tapered TSV based on the equation of current density, but the parasitic capacitance is not taken into account. Reference [8] uses conical models basis functions to extract the parasitics of tapered TSV with the consideration of frequency-dependent behavior, but the MOS effect is neglected in capacitance modeling. Although Reference [9] gives the closed-form expression for the capacitance of tapered TSV considering the MOS effect, its expression cannot capture the high frequency behavior. Therefore, the electrical model of tapered TSV in the above works is not comprehensive and cannot be used in the accurate analysis at high frequency.

    In this paper, a high frequency scalable tapered TSV electrical model considering the MOS effect and frequency-dependent behavior is proposed. Firstly, the analytical model of voltage-controlled MOS capacitance for tapered TSV is derived. Then, to capture the frequency-dependent behavior of tapered TSV, the high frequency parasitic of tapered TSV is extracted based on the conventional analytical equations of RLCG for two wire transmission lines. With the adoption of MOS capacitor model and equations of RLCG, a transmission line-type electrical model for tapered TSV is obtained. Finally, to verify the accuracy, the numerical results from the proposed model are compared with those from simulators.

2.   Voltage-controlled MOS capacitance analytical model for tapered TSV
  • Top cross-sectional view of single tapered TSV and a two-tapered TSV system are shown in Figure 1. Generally the central conductor of tapered TSV is copper. Then, the copper is surrounded by the Ta/TaN barrier layer, SiO$_{2}$ insulation layer and Si substrate successively. The barrier layer is used to avoid diffusion of Cu atoms, its thickness is only several tens of nanometers[10], which is far less than the radius of the Cu column. Therefore, the barrier layer is ignored in this paper for the MOS capacitance modeling. It can be observed from Figure 1(a) that TSV is a typical MOS structure, which comprises an oxide capacitance $C_{\rm ox}$ and a depletion capacitance $C_{\rm dep}$.

    Firstly, the oxide capacitance of tapered TSV is considered. As shown in Figure 1(b), the analytical model of oxide capacitance with the length of d$H$ can be expressed by Equation (1)[11]:
    ${\rm d}C_{\rm ox} =2\pi \varepsilon _{\rm ox} {\rm d}H/\ln \left\{ {1+{t_{\rm ox} }/{\left[{\tan \alpha \left( {H-h} \right)+a} \right]}} \right\}, $(1)
    where $a$ is the radius of the Cu column, $t_{\rm ox}$ is the thickness of the SiO$_{2}$ insulator, $h$ is the height of the TSV, $\varepsilon_{\rm ox}$ is the permittivity of the SiO$_{2}$, and $\alpha$ is the slope angle of the sidewall (as shown in Figure 1). The total oxide capacitance $C_{\rm ox}$ of the tapered TSV can be expressed approximately by integrating Equation~(1) from 0 to $h$:

    Equation (2) can also be used to model a cylindrical TSV when $a$ is zero. Then, we apply the method used for the planar MOS capacitor to model the tapered TSV depletion capacitance, but it is required to solve the Poisson equation in the cylindrical coordinate system. The one-dimensional (1D) Poisson's equation in the cylindrical coordinate system with a P-type Si substrate can be expressed as:
    $\frac{1}{r}\frac{\rm d}{{\rm d}r}\left[{r\frac{{\rm d}\phi (r)}{{\rm d}r}} \right]=\frac{qN_{\rm a} }{\varepsilon _{\rm si} }, $(3)
    where $N_{\rm a}$ is the P-type substrate doping concentration, $\varepsilon_{\rm si}$ is the permittivity of the Si, $\phi (r$) is the electrical potential as a function of the radius $r$, $w_{\rm dep}$ is the thickness of the depletion layer, and $q$ is the elementary charge. The corresponding boundary conditions can be expressed as:

    By solving Equation (3) with the boundary conditions given in Equation (4), we can obtain the following solution of the SiO$_{2}$-Si interface electric potential:

    Considering the SiO$_{2}$-Si interface state and the work function difference between the metal Cu and Si substrate, the expression for voltage exerted on the tapered TSV is derived as:
    $V_{\rm bias} =\phi _{\rm ms} +\phi (b)-\frac{2\pi bQ_{\rm eq} }{C_{\rm ox} }+\frac{\pi {\left[{\left( {b+w_{\rm dep} } \right)^2-b^2} \right]}qN_{\rm a} }{C_{\rm ox} }, $(6)
    where $Q_{\rm eq}$ is the equivalent interface charge, which is used to represent the effect of both the interface trapped and oxide charges, $\phi_{\rm ms}$ is the work function difference, $C_{\rm ox}$ is the oxide capacitance obtained from Equation (2), and $\phi (b)$ is the potential of the SiO$_{2}$-Si interface obtained from Equation (4). It can be seen that the thickness of depletion layer $w_{\rm dep}$ can be determined by solving Equations (5) and (6) simultaneously if the values of $C_{\rm ox}$ and $V_{\rm bias}$ are both given. For the maximum depletion condition, the maximum thickness of the depletion layer can be obtained from Equation (5) when the $\phi (b)$ is fixed at ($2k_{\rm B}T/q)$ln($N_{\rm a}$/$n_{\rm i}$). Once the $w_{\rm dep}$ is worked out, the depletion capacitance $C_{\rm dep}$ of tapered TSV can be obtained by the integral method used in Equation (1), $C_{\rm dep}$ can be expressed as:

    Because the oxide capacitance and depletion capacitance are connected in series, the MOS capacitance $C_{\rm mos}$ is finally derived as:

    Using Equation (8), we can obtain the voltage-controlled property of MOS capacitance for tapered TSV, because the $w_{\rm dep}$ is a function of the bias voltage $V_{\rm bias}$ in our analytical model. Similarly, the MOS capacitance of tapered TSV surrounded by an N-type Si substrate can also be obtained, it is only needed to change the corresponding items of above equations into negative.

3.   Transmission line-type electrical model for tapered TSV

    3.1.   The analytical equations of RLCG considering the frequency-dependent behavior

  • Because the two-wire system has been widely studied in the microwave field, the high frequency characteristics of TSV can also be studied by the adoption of the two-TSV system, as shown in Figure 1(b), one tapered TSV is a signal via and the other a ground via. However, unlike the two-wire system, the dielectric between two tapered TSVs is a multilayered structure (SiO$_{2}$-Si-SiO$_{2})$ whose parasitic effects are more complex. The parasitic components of the two-TSV system include the resistance, inductance and capacitance. Hence it is very important to extract these parasitics accurately before the establishment of a tapered TSV electrical model. The analytical model of MOS capacitance is derived in the previous section, while the rest of the parasitic components can be extracted based on the formulas in References [12, 13] used for the two-wire transmission line system:
    $R=\frac{h\sqrt {\pi f\mu_0/\sigma _{\rm c} } }{\pi a\sqrt {1-(2a/d)^2} }, $(9)
    $L =\mu _0 h\arccos {\rm h}(d/2a)/\pi , $(10)
    $C =\pi \varepsilon _{\rm si} h/\arccos {\rm h}[d/2(b+w_{\rm dep})], $(11)
    $G=\pi \sigma _{\rm si} h/\arccos {\rm h} [d/2(b+w_{\rm dep})], $(12)
    where $f$ is the frequency, and $d$ denotes the center-to-center distance of two tapered TSVs. The $\mu_{0}$, $\sigma_{\rm si}$ and $\sigma_{\rm c}$ represent the free space permeability, the conductivity of the silicon substrate and the conductivity of the Cu column respectively. However, the above equations are only suitable for a cylindrical TSV without a slope angle. Moreover, apart from the $R$, all the other expressions of LCG cannot fully capture the frequency-dependent behavior for lack of a frequency item. As the frequency increases, the effects of the conductor loss and dielectric loss may not be characterized accurately by the above expressions. Therefore, before being applied to build the high frequency tapered TSV electrical model, the above expressions of RLCG need to be revised.

    (1) Resistance and inductance of tapered TSV

    The skin effect drives the current around the outer edge of the TSV, and the proximity effect draws the current to the inner edges of the adjacent TSVs. Both effects have a great impact on the resistance and inductance of the TSV at high frequency. To model the resistance and inductance of the tapered TSV, we can also use the integral method based on Equations (9) and (10). The analytical model of resistance for the tapered TSV with the length of d$H$ can be expressed by Equation (13).

    Replacing item $a$ in Equation (9), item tan$\alpha $($x-H$) $+$ $a$ in Equation (13) denotes the radius of the tapered TSV with the length of d$H$. Therefore, the total resistance $R_{\rm tsv}$ of the tapered TSV can be expressed approximately by integrating Equation (13) from 0 to $h$:
    \begin{split} \label{eq14} {}& R_{\rm tsv} = \int_0^h \\& {\frac{h\sqrt {\pi f\mu_0/\sigma _{\rm c}}{\rm d}H} {\pi \left[{\tan \alpha({x-H})+a} \right]\sqrt {1-\left\{ {2\left[{\tan \alpha ({x-H})+a} \right]/d} \right\}^2} }} .\end{split}(14)
    As the frequency increases, the value of inductance decrease, so actually the $L$ is dependent on frequency. To capture the frequency-dependent behavior of inductance for tapered TSV, we use the same method that is used in the derivation of resistance for tapered TSV. The item tan$\alpha (x-H)$ $+$ $a$ is also used to characterize the radius of tapered TSV with the length of d$H$. Hence, the inductance of tapered TSV can be expressed as:
    \begin{split} \label{eq15} L_{\rm tsv} ={}& \int_0^h \left( \mu _0 \arccos {\rm h} \left\{ \frac{d}{2\left[\tan \alpha \left( x-H \right)+a\right]} \right\}\right. \\[2mm]& \left. \times\, \pi^{-1} +\frac{R_{\rm tsv}}{2\pi f} \right) {\rm d}H, \end{split}(15)
    where $L_{\rm tsv}$ is the revised inductance of tapered TSV, and $R_{\rm tsv}$ is the resistance of tapered TSV, which can be obtained from Equation (7). Because the inductance and resistance of the transmission line have a frequency-dependent relationship with each other[14], the item $R_{\rm tsv}$/2$\pi f$ can characterize this relationship and be applied to capture the frequency-dependent behavior of inductance of tapered TSV.

    (2) Capacitance and conductance of tapered TSV

    The capacitance between two TSVs is consisting of MOS capacitance and substrate capacitance; MOS capacitance was derived in the previous section, the substrate capacitance will be considered next. The substrate is the semiconductor material whose feature is between a conductor and an insulator. It means that the signal propagating through the substrate can cause the polarization loss and the conductor loss simultaneously at high frequency. To characterize the above two lossy effects, the complex permittivity should be brought into the expression of $C$ in Equation (11). According to Maxwell's equations, the relationship between magnetic field $H$ and electric field $E$ in the substrate can be expressed by the following equation:
    $\nabla H=\sigma _{\rm si} E+{\rm j}\omega(\varepsilon _{\rm si} -{\rm j}\varepsilon _{\rm si}^{"} )E={\rm j}\omega[\varepsilon _{\rm si} -{\rm j}(\varepsilon _{\rm si}^{"} +\sigma _{\rm si} /\omega)]E, $(16)
    where $\omega$ is the angular frequency, and $\varepsilon_{\rm si}$ - j($\varepsilon_{\rm si}^{"}$ $+$ $\sigma_{\rm si}/\omega)$ is the complex permittivity of silicon substrate. The item $\sigma_{\rm si}/\omega$ is used to account for the conductor loss, and the item $\varepsilon_{\rm si}^{"}$ is used to account for the polarization loss. The $\varepsilon_{\rm si}^{"}$ can also be written as $\varepsilon_{\rm si}^{"}$ $=$ tan$\delta_{\rm si}$$\cdot $$\varepsilon_{\rm si}$, and the tan$\delta_{\rm si}$ is the loss tangent of silicon substrate. Substituting the complex permittivity of silicon for the original permittivity in Equation (11), the revised substrate capacitance with length of d$H$ can be expressed by

    With the method of integral, the total substrate capacitance can be expressed approximately by integrating Equation (17) from 0 to $h$:

    The mixed dielectric layer between two TSVs is a multilayer structure, therefore, the total capacitance of a two-tapered TSV system is composed of three capacitances in a series including the two MOS capacitances and one substrate capacitance. With Equations (8) and (18), the total capacitance of the two-tapered TSV system can be expressed by the following equation:

    To characterize the dielectric loss effect, Equation (19) should be changed into a complex admittance formula:
    ${\rm j}\omega C_{\rm tsv} =G_{\rm tsv} ^\ast +{\rm j}\omega C_{\rm tsv} ^\ast, $(20)
    where the $G_{\rm tsv}^{\ast}$ is used to account for the equivalent dielectric loss, and the $C_{\rm tsv}^{\ast}$ is the total equivalent capacitance. Due to the existence of $\omega$, the expression of $G_{\rm tsv}^{\ast}$ and $C_{\rm tsv}^{\ast}$ can capture the frequency-dependent behavior. With the $G_{\rm tsv}^{\ast}$ and $C_{\rm tsv}^{\ast}$, both the dielectric loss effect and MOS effect can be fully captured for the two-tapered TSV system. Until now, all the expressions of parasitic components were analytically calculated considering the frequency-dependent behavior and MOS effect.

  • 3.2.   Transmission line-type electrical model for tapered TSV

  • Actually, with the relation of wavelength versus frequency ($\lambda$ $=$ $v/f$), we know that the wavelength (0.87 mm at 100 GHz) is longer than the height of tapered TSV (generally about dozens of micrometers). Therefore, the lump model is sufficient to capture the high frequency characteristic of tapered TSV. Figure 2 shows a lumped element circuit model of the previously mentioned two-tapered TSV system. Due to the topology of the proposed model being similar to the topology of the first-order model of the transmission line, we call it a transmission line-type electrical model.

    Once the specific physical parameters of tapered TSV are all given, the values of $R_{\rm tsv}$, $L_{\rm tsv}$, $C_{\rm tsv}^{\ast}$ and $G_{\rm tsv}^{\ast}$ can be extracted with the proposed analytical equations in Section 3.1. Each RLCG equation is revised and is a function of the variables from the physical parameters of the tapered TSV structure. Therefore, the above model with $R_{\rm tsv}L_{\rm tsv}C_{\rm tsv}^{\ast}G_{\rm tsv}^{\ast}$ is a high frequency and scalable electrical model. To prove that the transmission line-type electrical model has the scalability, we also apply it into the three-tapered TSV system--one signal is in the middle and two grounds on both sides (GSG). The three-TSV system electrical model is shown in Figure 3. These two electrical models will be validated in the next section.

4.   Result and verification

    4.1.   Verification of the MOS capacitance analytical model

  • The MOS capacitance analytical model is verified by simulation with the TCAD tool--Sentaurus Device[15]. The physical parameters of the tapered TSV structure involved in the simulation are as follows: $a$ is 5 $\mu $m, $d$ is 100 $\mu $m, $t_{\rm ox}$ is 0.2~$\mu $m, $h$ is 50 $\mu $m, $\alpha$ is 1$^\circ$, 3$^\circ$ and 5$^\circ$ respectively. The material properties are $\sigma_{\rm c}$ $=$ 5.8 $\times$ 10$^{7}$ S/m, $\varepsilon_{\rm si}$ $=$ 11.9 $\times$ 8.85 $\times$ 10$^{-6}$ F/$\mu $m, $\varepsilon_{\rm ox}$ $=$ 4 $\times$ 8.85 $\times$ 10$^{-6}$ F/$\mu $m, and tan$\delta _{\rm si}$ $=$ 0.02. The substrate is P-type, the doping concentration $N_{\rm a}$ is 1.25 $\times$ 10$^{15}$ cm$^{-3}$, the work function difference $\phi_{\rm ms}$ is $-0.65$ eV, $\sigma_{\rm si}$ is 10 s/m, and $Q_{\rm eq}$ is 5 $\times$ 10$^{10}$ cm$^{-2}$.

    As shown in Figure 4, the values of MOS capacitance calculated by the proposed analytical model with Mathematica[18] are compared with TCAD simulation's at 1 MHz. It can be seen that the analytical results agree with the simulation results, and the voltage-dependent behavior of MOS capacitance can also be fully captured. The comparison confirms that the MOS capacitance model in this work can be used to accurately characterize the MOS effect of tapered TSV with different slope angles.

    It is noted that the MOS capacitance in Figure 5 does not follow the conventional inversion curve as the voltage continues to rise. This is because at high frequency ($\geqslant $ 1 MHz), the generation/recombination of inversion carriers cannot follow the fast signals[16]. As a result, the MOS capacitance keeps a fully depleted state in which the radius of the depletion region achieves maximum and the MOS capacitance becomes constant around 1 V (see Figure 5). Due to the fact that the power supply voltage of a digital system usually ranges from 0 to 1~V, the MOS capacitance can be assumed to be in a fully depleted state, and be approximated by a constant at high frequency. Moreover, we can also find out that as slope angle $\alpha$ increases, the total MOS capacitance $C_{\rm mos}$ decreases. The crosstalk, mainly induced by capacitive coupling, will be lower in tapered TSV with a large slope angle than that with a small slope angle. The crosstalk phenomenon can be improved by increasing the slope angle appropriately.

  • 4.2.   Verification of the analytical equations of RLCG

  • To validate the proposed analytical equations of $R_{\rm tsv}\times L_{\rm tsv} C_{\rm tsv}^{\ast}G_{\rm tsv}^{\ast }$, the EM simulation with 3D filed solver HFSS is performed[17]. According the analysis of MOS capacitance in the previous section, we assume MOS capacitance keeps a fully depleted state, and is minimum and constant in our verification. From the EM simulations, $Z$ and $Y$ parameters are extracted and used to obtain the simulation results of $R_{\rm tsv} L_{\rm tsv} C_{\rm tsv}^{\ast}G_{\rm tsv}^{\ast}$, as shown in Equations (19)-(22)[19].
    $R_{\rm tsv \_{\rm simulation}}=-{\rm Re}(1/Y_{21}), $(21)
    $L_{\rm tsv\_{\rm simulation}}=-{\rm Im}(1/Y_{21})/\omega, $(22)
    $C_{\rm tsv\_simulation}^\ast={\rm Im}(1/Z_{21})/\omega, $(23)
    $G_{\rm tsv\_simulation}^\ast={\rm Re}(1/Z_{21}), $(24)
    where $Y_{21}$ and $Z_{21}$ are the transfer admittance and transfer impedance of a two-port network respectively. Items "Re" and "Im" denote the real part and imaginary part of a value respectively. The above two parameters are both obtained from the HFSS simulation. Then we use Equations (19)-(22) to calculate the simulation results of $R_{\rm tsv} L_{\rm tsv} C_{\rm tsv}^{\ast}G_{\rm tsv}^{\ast }$.

    As shown in Figure 5, the values of $R_{\rm tsv}L_{\rm tsv} C_{\rm tsv}^{\ast }G_{\rm tsv}^{\ast }$, calculated by the proposed analytical equations with Mathematica in Section 3, are compared with those obtained from the EM simulations. The results show that there is a good match between the HFSS simulation and analytical equations from 1 to 100 GHz. All the expressions of parasitic components can capture the frequency-dependent behavior of tapered TSV with different slope angles.

    Due to the volume of TSV decreasing with the increase of the slope angle, the resistance and inductance of tapered TSV will be larger with a large slope angle, as shown in Figure 5(a) and 5(b). However, the difference between different slope angles is small in equivalent capacitance and conductance of tapered TSV. The reason is that the equivalent capacitance and conductance largely depend on the distance of the two-tapered TSVs.

  • 4.3.   Verification of the transmission line-type electrical model

  • To verify the transmission line-type electrical model, the scattering parameters $S_{21}$ obtained from the proposed model are compared with the HFSS simulation. As shown in Figure 6, the insertion loss $S_{21}$ magnitude of the two-tapered TSV system and the three-tapered TSV system obtained from the proposed model and HFSS simulation both show good correlation from 1 to 100 GHz. The comparison confirms that the model in this work is accurate over a wideband frequency. Due to the scalability, the proposed model can be applied in the modeling of a multi-tapered TSV system or multi-port-tapered TSV networks in 3D IC.

    From Figure 6, we can see that the insertion loss increases with the increase of the slope angle. This phenomenon could be due to the increase of conductance loss. From Figure 5, we know that the resistance and inductance of tapered TSV increases more obviously than the capacitance and conductance. Therefore, the insertion loss most likely is caused by the conductance loss of tapered TSV. Therefore, the insertion loss will be more serious in tapered TSV with a large slope angle.

5.   Conclusion
  • In this paper, a transmission line-type electrical model for tapered TSV was proposed by adopting the MOS capacitance and revising RLCG equations. The results of the model in this work were verified against simulations from 1 to 100 GHz. The verification results indicate that the parasitic components of RLCG are strongly dependent on the frequency, and the slope angle of tapered TSV has a great impact on the insertion loss. Hence, in the real application, it needs to make a compromise between the facility of the subsequent process and the performance of the 3D IC system.

    With the proposed model, the high frequency characteristic and semiconductor phenomenon can be fully captured. In addition, because the proposed model is scalable, it can be used to model the multi-port tapered TSV networks for further study.

Figure (6)  Table (15) Reference (19) Relative (20)

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