Ultralow specific on-resistance high voltage trench SOI LDMOS with enhanced RESURF effect

    Corresponding author: Xiaorong Luo, xrluo@uestc.edu.cn
  • State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, China

Key words: RESURF-enhancedmultiple-directional depletion effectsilicon-on-insulatorbreakdown voltagespecific on-resistance

Abstract: A RESURF-enhanced high voltage SOI LDMOS (ER-LDMOS) with an ultralow specific on-resistance (Ron,sp) is proposed. The device features an oxide trench in the drift region, a P-pillar at the sidewall of the trench, and a buried P-layer (BPL) under the trench. First, the P-pillar adjacent to the P-body not only acts as a vertical junction termination extension (JTE), but also forms a vertical reduced surface field (RESURF) structure with the N-drift region. Both of them optimize the bulk electric field distributions and increase the doping concentration of the drift region. Second, the BPL together with the N-drift region and the buried oxide layer (BOX) exhibits a triple-RESURF effect, which further improves the bulk field distributions and the doping concentration. Additionally, multiple-directional depletion is induced owing to the P-pillar, the BPL, and two MIS-like structures consisting of the N-drift region combined with the oxide trench and the BOX. As a result, a significantly enhanced-RESURF effect is achieved, leading to a high breakdown voltage (BV) and a low Ron,sp. Moreover, the oxide trench folds the drift region in the vertical direction, resulting in a reduced cell pitch and thus Ron,sp. Simulated results show that the ER-LDMOS improves BV by 67% and reduces Ron,sp by 91% compared with the conventional trench LDMOS at the same cell pitch.


1.   Introduction
  • Silicon-on-insulator (SOI) lateral double-diffused metal-oxide-semiconductor (LDMOS) transistors are widely used in smart power integrated circuits due to their easy integration and effective isolation[1, 2]. For the conventional LDMOS, a long and lightly doped drift region is needed to achieve a high breakdown voltage (BV), which results in an unexpected high specific on-resistance ($R_{\rm on, sp})$[3, 4]. The junction termination extension (JTE) and reduced surface field (RESURF) technology have been widely adopted to alleviate the inherent contradiction between BV and $R_{\rm on, sp}$[5, 6, 7, 8]. In the trench LDMOS, an oxide trench in the drift region folds the drift region in the vertical direction, leading to a reduced cell pitch and thus sharply decreasing the $R_{\rm on, sp}$ without sacrificing the BV[9, 10, 11]. Combining the RESURF principle with the trench technology, the LDMOS can obtain a high BV as well as a low $R_{\rm on, sp}$ simultaneously[12, 13, 14, 15]. Unfortunately, the RESURF effect is weakened in the conventional deep trench LDMOS, resulting in a low drift region doping concentration and low electric field (E-field) strength in the Si region around the bottom of the oxide trench. Therefore, the conventional deep trench is not suitable for high-voltage power applications.

    In this paper, a novel ultralow specific on-resistance high voltage trench SOI LDMOS with an enhanced RESURF effect (ER-LDMOS) is proposed. This device is characterized by an oxide trench, a P-pillar beside the trench, and a buried P-layer (BPL) under the trench. The JTE and RESURF technology in combination with the trench technology are applied to improve the trade-off between the BV and $R_{\rm on, sp}$. Simulated results show that the ER-LDMOS exhibits significant enhancement in the BV and reduction in the $R_{\rm on, sp}$ compared with the conventional trench SOI LDMOS (C-LDMOS) and the trench SOI LDMOS only with a P-pillar (P-LDMOS).

2.   Structure and mechanism
  • Figure 1(a) shows the schematic cross-section view of the ER-LDMOS structure. It has three key features: an oxide trench introduced into the drift region, a P-pillar at the sidewall of the trench, and a BPL under the trench. $W_{\rm t}$ and $D_{\rm t}$ are the width and depth of the oxide trench. $t_{\rm s}$, $t_{\rm ox}$ and $t_{\rm bp}$ represent the thickness of the SOI layer, the buried oxide layer (BOX) and the BPL, respectively. $t_{1}$ is the gap between the trench and the BPL. $W_{\rm p}$ is the width of the P-pillar. $N_{\rm p}$, $N_{\rm bp}$ and $N_{\rm d}$ are the doping concentration of the P-pillar, the BPL and the drift region, respectively. The $x$- and $y$-directions are shown in Figure 1(a).

    It is well known that the off-state BV of the LDMOS is determined by the minimum of the lateral BV (BV$_{\rm lat})$ and vertical BV (BV$_{\rm ver})$. For the ER-LDMOS, the BV is limited by the BV$_{\rm lat}$ (i.e. BV $=$ BV$_{\rm lat}$ < BV$_{\rm ver}$). Figure 1(b) gives a schematic diagram of the vertical potential distributions under the source and drain for the ER-LDMOS. First, the applied drain voltage ($V_{\rm D})$ is shared by the Si layer and the BOX under the drain (called $V_{\rm Si, D}$ and $V_{\rm I})$, and the $V_{\rm D}$ is given by

    Second, the voltage shared by the BOX is equal to the voltage sustained by the Si layer under the source (called $V_{\rm Si, S})$ because both the source and substrate are grounded (i.e., $V_{\rm Si, S}=V_{\rm I}$, and thus $V_{\rm D}=V_{\rm Si, D}+V_{\rm Si, S}$) as shown in Figure 1(b). Third, the sum of the voltages sustained respectively by the Si layer under the source and under the drain at breakdown is BV$_{\rm lat}$ (see Figure 2). Therefore, the BV of the ER-LDMOS can be written as

    Figures 2(a)-2(c) show the equipotential contour distributions of the ER-LDMOS, P-LDMOS and C-LDMOS at breakdown, respectively. The double-headed arrows denote the voltage drops under the source and drain. Firstly, the P-pillar, extending from the P-body to the bottom of the trench, not only acts as a vertical JTE, but also builds a vertical RESURF structure with the N-type drift region. As a result, the E-field distributions of the silicon layer under the source are modulated and thus improve the $V_{\rm Si, S}$. The $V_{\rm Si, S}$ values are 310 V and 336~V for the ER-LDMOS and P-LDMOS respectively in Figures 2(a) and 2(b), while it is just 159 V for the C-LDMOS in Figure 2(c). Secondly, the BPL in the N-drift region and the BOX of the ER-LDMOS exhibit a triple-RESURF effect, and thereby optimize the E-field distributions below the trench and under the drain, resulting in an improvement in $V_{\rm Si, D}$. This is demonstrated by comparing the $V_{\rm Si, D}$ in Figures 2(a) and 2(b). The $V_{\rm Si, D}$ of the ER-LDMOS increases to 375 V from 275 V of the P-LDMOS, with an increment of 100 V. Although the small non-depleted regions exist in the drift region as shown in Figure 2(a), the BV does not deteriorate because the E-field is inherently very low near these regions[15].

    In the $x$-direction, the oxide trench is built into the drift region to improve the lateral E-field ($E_{x})$. In the Si/trench-oxide interface, according to the equation $\varepsilon_{\rm s}E_{\rm s}=\varepsilon_{\rm ox}E_{\rm ox}$, the BV$_{\rm lat}$ of the ER-LDMOS is sustained mainly by the oxide trench, which is given by
    ${\rm BV}_{\rm lat}\approx E_{\rm tox}W_{\rm t}=\frac{\varepsilon_{\rm s}E_{\rm s}W_{\rm t}}{\varepsilon_{\rm ox}}, $(3)
    where $E_{\rm s}$ and $E_{\rm tox}$ are the E-field strength of the Si and oxide trench in the interface, and $\varepsilon_{\rm s}$ and $\varepsilon_{\rm ox}$ are their relative permittivities, respectively. Due to $\varepsilon_{\rm s}=3\varepsilon_{\rm ox}$ and accordingly $E_{\rm ox}=3E_{\rm s}$, the oxide trench increases the BV$_{\rm lat}$ for a given cell pitch. Furthermore, the modulation effects of the P-pillar and the BPL could enhance the $E_{\rm s}$, and improve the $E_{\rm tox}$ and BV$_{\rm lat}$ accordingly. Moreover, the voltage drop at the surface (i.e. along the N $\to$ M direction) is equal to that in Si around the trench (i.e. along the N $\to$ C $\to$ B $\to$ M direction), as is shown in Figure 2(a). It proves that the oxide trench folds the drift region in the $y$-direction, resulting in reduced cell pitch and $R_{\rm on, sp}$.

    In the off-state, two metal-insulator-semiconductor (MIS)-like structures (i.e. source electrode/oxide trench/SOI layer and N-sub/BOX/SOI layer) together with the P-pillar and the BPL cause multiple-directional depletion of the drift region. The multiple-directional depletion effect leads to an enhanced RESURF effect[12], which not only reshapes the bulk E-field distributions, but also increases the drift region doping concentration, resulting in an improved BV and a reduced $R_{\rm on, sp}$.

3.   Results and discussion
  • The electric characteristics of the ER-LDMOS are calculated by the 2-D simulator MEDICI. The physical models of IMPACT.I, AUGER, FLDMOB, CONSRH, CCSMOB and BGN are mainly used in the simulation. The device structure parameters used in the simulations are as follows: $W_{\rm t}$ $=$ 9 $\mu $m, $D_{\rm t}$ $=$ 18 $\mu $m, $t_{\rm s}$ $=$ 23 $\mu $m, $t_{\rm ox}$ $=$ 1 $\mu $m, $W_{\rm p}$ $=$ 0.5 $\mu $m, $t_{\rm bp}$ $=$ 1 $\mu $m and $t_{1}$ $=$ 2.5 $\mu $m. The width of the BPL is equal to $W_{\rm t}$. The cell pitch is 15 $\mu $m. The dimension parameters used in the P-LDMOS and C-LDMOS are the same as those of the ER-LDMOS.

    Figure 3(a) shows the E-field component distributions in Si around the trench of the three devices. The off-state BV is determined by the area enclosed by the E-field line and the lateral axis, which can be expressed as
    ${\rm BV}=\int^{\rm B}_{\rm M}\vert E_{y{\rm MB}}\vert +\int^{\rm C}_{\rm B} \vert E_{x{\rm BC}}\vert +\int^{\rm N}_{\rm C} E_{y{\rm NC}}, $(4)
    where the $E_{y{\rm MB}}$, $E_{x{\rm BC}}$ and $E_{y{\rm NC}}$ are the E-field components along the M$\to $B, B$\to $C and N$\to $C directions, respectively. As shown in Figure 3(a), two new E-field peaks are induced at points B and C for both ER-LDMOS and P-LDMOS, and thus the average bulk field is improved. The P-pillar not only reduces the E-field peak at point A so as to prevent the premature breakdown, but also causes an E-field peak at point B, leading to more uniform vertical E-field ($E_{y})$ distributions and a higher E-field strength in the SOI layer under the source. However, the E-field under the source of the C-LDMOS is very low, as shown in Figures 3(a) and 3(b). The shaded area $\Delta V_{\rm Si, S}$ in Figure 3(b) represents the significant increment in $V_{\rm Si, S}$ of the ER-LDMOS compared with that of the C-LDMOS. Furthermore, the BPL not only raises the E-field around point C, as shown in Figure 3(a), but also enhances the vertical E-field component in the SOI layer under the drain, as shown in Figure 3(c). The vertical average $E_{y}$ of ER-LDMOS under the drain is increased to 1.6 $\times$ 10$^{5}$ V/cm from 1.2 $\times$ 10$^{5}$ V/cm of the P-LDMOS and 1.1 $\times$ 10$^{5}$ V/cm of the C-LDMOS. The corresponding increments in $V_{\rm Si, D}$ are thus about 100 V and 125 V, as shown in Figure 3(d). The $V_{\rm I}$ is equal to $V_{\rm Si, S}$, which is consistent with the description in the above section. The $V_{\rm Si, D}$ and $V_{\rm Si, S}$ of the ER-LDMOS are much higher than those of the C-LDMOS.

    Figures 4(a) and 4(b) give the E-field distributions along the surface and in the BOX, respectively. The $E_{\rm tox}$ of both the ER-LDMOS and P-LDMOS are much higher than that of the C-LDMOS because of the E-field modulation effect introduced by the P-pillar, as shown in Figure 4(a). The BPL further increases the $E_{\rm tox}$. Consequently, the surface average $E_{\rm tox}$ of the ER-LDMOS increases from 4.5 $\times$ 10$^{5}$ V/cm of the C-LDMOS to 7.5 $\times$ 10$^{5}$ V/cm. In the Si/BOX interface, the Gauss law is expressed as $\varepsilon_{\rm s} E_{\rm s}=\varepsilon_{\rm ox} E_{\rm ox}+q \sigma_{\rm s}$, where the $E_{\rm box}$ is the E-field strength of the BOX, and $\sigma_{\rm s}$ is the carrier density on the BOX interface. In the off-state, substantial holes and electrons are induced in the top and bottom interface of the BOX, resulting in $E_{\rm ox} \gg 3 E_{\rm s}$ as depicted in Figure 4(b). The mechanism of the thin BOX with carriers in the interface sustaining a high blocking voltage has already been well studied[14, 15]. Owing to the strong bulk E-field modulation effect, the $E_{\rm box}$ of the ER-LDMOS and P-LDMOS are increased to 344~V/$\mu $m and 318 V/$\mu $m respectively, while the $E_{\rm box}$ of the C-LDMOS is just 165 V/$\mu $m. In comparison with the P-LDMOS, the BPL in the ER-LDMOS enhances the $V_{\rm Si, D}$ and reduces the $V_{\rm I}$, as illustrated in Figures 2, 3(d) and 4(b).

    Figure 5(a) gives the influences of $N_{\rm d}$ on BV for the ER-LDMOS as the functions of $N_{\rm p}$ or $N_{\rm bp}$. The circled points show the optimal BVs. For a given $N_{\rm bp}$ (or $N_{\rm p})$, the charge compensation between the N-drift region and the P-pillar and/or buried P-layer makes the optimal $N_{\rm d}$ increase with the increasing $N_{\rm p}$ (or $N_{\rm bp})$, as shown in Figure 5(a). For a given $N_{\rm p}$ and $N_{\rm bp}$, the BV increases first and then decreases with the increasing $N_{\rm d}$ because of the RESURF effect. In the optimized cases, the values of $N_{\rm p}$ and $N_{\rm bp}$ are 3.0 $\times$ 10$^{16}$ cm$^{-3}$ and 1.5 $\times$ 10$^{16}$ cm$^{-3}$, respectively.

    The space between the BPL and oxide trench in the ER-LDMOS has an impact on the BV and $R_{\rm on, sp}$, as illustrated in Figure 5(b). The optimal $N_{\rm d}$ values for different $t_{\rm 1}$ are also given. Both too small and too large $t_{\rm 1}$ values deteriorate the enhanced RESURF effect and result in low $N_{\rm d}$ values. Thus the BV and $R_{\rm on, sp}$ are scarified accordingly. The maximum BV appeared at $t_{\rm 1}$ $=$ 2.5 $\mu $m and the optimized $N_{\rm d}$ values for different $t_{1}$ are also labeled in Figure 5(b) at $D_{\rm t}$ $=$ 18 $\mu $m and $t_{\rm s}$ $=$ 23 $\mu $m. The optimal range for $t_{1}$ is 1-3 $\mu $m, which implies that $t_{1}$ has a good process tolerance.

    Figure 6 shows the dependences of BV and $R_{\rm on, sp}$ on $N_{\rm d}$ for the three devices above. The BV of 685 V for the ER-LDMOS is improved by 12 % and 67 % compared with those of the P-LDMOS and C-LDMOS. The $R_{\rm on, sp}$ monotonically decreases as the $N_{\rm d}$ increases. Owing to the multiple-directional depletion effect and the enhanced RESURF effect, the optimal $N_{\rm d}$ of the ER-LDMOS reaches 3.2 $\times$ 10$^{15}$ cm$^{-3}$, while $N_{\rm d}$ values are 1.8 $\times$ 10$^{15}$ cm$^{-3}$ and 2 $\times$ 10$^{14}$ cm$^{-3}$ for the P-LDMOS and C-LDMOS, respectively. Compared with the P-LDMOS, the ER-LDMOS reduces $R_{\rm on, sp}$ by 41 % at the optimal cases. Even at the same breakdown voltage level, the $R_{\rm on, sp}$ of the ER-LDMOS can also be reduced by 20 % compared with that of the P-LDMOS. The RESURF effect of the C-LDMOS is nevertheless particularly weak due to a too deep trench, leading to a significantly high $R_{\rm on, sp}$ (see Table 1).

    Table 1 lists several optimized device parameters for the ER-LDMOS, P-LDMOS and C-LDMOS. The ER-LDMOS exhibits the highest figure-of-merit (FOM $=$ BV$^2$/$R_{\rm on, sp}$) of 10.5 MW/cm$^{2}$, which is twice as high as that of the P-LDMOS. However, the FOM of the C-LDMOS is only 0.3 MW/cm$^{2}$. Figure 7 compares the $R_{\rm on, sp}$ versus BV between the ER-LDMOS and the conventional RESURF LDMOSs (single-, double-, and triple-) shown in Reference [16]. The $R_{\rm on, sp}$ decreases by 50 % at the applied voltage level of 600 V and the BV increases by 41 % at the $R_{\rm on, sp}$ level of 45 m$\Omega$$\cdot$cm$^{2}$ compared with the triple-RESURF LDMOSFETs. Obviously, the ER-LDMOS achieves the best improvement in the trade-off relation between BV and $R_{\rm on, sp}$.

    Figure 8 compares the dynamic performances of the ER-LDMOS and P-LDMOS at the BV level of 600 V. The turn-off speed of the ER-LDMOS is slower than that of the P-LDMOS, but the turn-on speed is faster and the total switching delay is almost the same. Apparently, for high voltage ICs where high frequency switching is not the most important, the ER-LDMOS exhibits superior static performance, as shown in Table 1.

    The key process steps to manufacture the ER-LDMOS are given in Figure 9. The process flow begins with the BPL implantation on the N-type SOI wafer and followed by forming the N-drift epitaxial region. Subsequently, an oxide trench etch is performed. Then a P-pillar is formed by titled implantation. In order to control the implantation width, BF$_{2}$ is preferred as the p-type dopant source because of its low diffusion coefficient. After the titled implantation, the trench is filled by oxide deposition, followed by planarization, as shown in Figure 9(e). In Figure 9(f), a trench gate is formed, including gate trench etching, hydrogen-oxygen synthesis oxidation to form the gate oxide, and the gate trench refilling with polysilicon. Finally, the body, source, and drain regions as well as electrodes are formed, as illustrated in Figures 9(g) and 9(h).

4.   Conclusion
  • An ultralow specific on-resistance high voltage trench SOI LDMOS with a P-pillar and a BPL near the oxide trench is proposed and studied by simulation. The RESURF-enhanced effect and multiple-dimensional depletion effect are introduced by the P-pillar, the BPL and two MIS-like structures built by the N-drift region combined with the oxide trench and the BOX. Both of them optimize the bulk E-field distributions and improve the drift region doping concentration, leading to a high BV of 685 V and a low $R_{\rm on, sp}$ of 44.5 m$\Omega $$\cdot$cm$^{2}$. Compared with those of the P-LDMOS and C-LDMOS, the BV of the ER-LDMOS is improved by 12 % and 67 %, and the $R_{\rm on, sp}$ is reduced by 41 % and 91 % respectively. The proposed device exhibits a better trade-off between BV and $R_{\rm on, sp}$ compared with the single-, double- and triple-RESURF devices.

Figure (9)  Table (3) Reference (16) Relative (20)

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