Design of a high linearity and high gain accuracy analog baseband circuit for DAB receiver

Key words: complex filterautomatic tuningPGAreceiverDABDCOC

Abstract: An analog baseband circuit of high linearity and high gain accuracy for a digital audio broadcasting receiver is implemented in a 0.18-μm RFCMOS process. The circuit comprises a 3rd-order active-RC complex filter (CF) and a programmable gain amplifier (PGA). An automatic tuning circuit is also designed to tune the CF's pass band. Instead of the class-A fully differential operational amplifier (FDOPA) adopted in the conventional CF and PGA design, a class-AB FDOPA is specially employed in this circuit to achieve a higher linearity and gain accuracy for its large current swing capability with lower static current consumption. In the PGA circuit, a novel DC offset cancellation technique based on the MOS resistor is introduced to reduce the settling time significantly. A reformative switching network is proposed, which can eliminate the switch resistor's influence on the gain accuracy of the PGA.The measurement result shows the gain range of the circuit is 10—50 dB with a 1-dB step size, and the gain accuracy is less than ± 0.3 dB. The OIP3 is 23.3 dBm at the gain of 10 dB. Simulation results show that the settling time is reduced from 100 to 1 ms. The image band rejection is about 40 dB. It only draws 4.5 mA current from a 1.8 V supply voltage.


1.   Introduction
  • The digital audio broadcasting (DAB) system is the 3rd generation sound broadcasting system, which provides a much higher sound quality than traditional broadcast, as well with a high spectrum and power efficiency[1]. A highly integrated DAB receiver is necessary to promote DAB's development.

    The RF front-end of the DAB receiver proposed is a low-IF architecture, which has relatively low power dissipation and high integration capability[2]. Figure 1 shows its block diagram. The main disadvantage of low-IF architectures is that the image signal cannot be filtered before the mixer. To resolve this problem, a CF is an effective solution. As shown in Figure 2, shifting the transfer function of the low pass filter (LPF) prototype by $\omega_{0}$, then the transfer function of the CF is obtained[3].

    Because of the $g_{\rm m}$-$C$ topology's poor linearity, an active-RC topology CF is preferred. The CF is cascaded by a PGA consisting of three gain stages based on a closed-loop feedback topology to expand the dynamic range of the circuit[4]. To improve the linearity of the circuit, a class-AB FDOPA is designed. Compared to the class-A FDOPA, the push-pull operation of the class-AB output stage will provide a large output current. The PGA features a novel DCOC circuit using MOS transistors that work in the cutoff region and improve integration capability. The new proposed switching network enhances the gain accuracy effectively. The CF's ATC cancels the frequency offset due to PVT (process, voltage, and temperature) variations based on the RC time constant, which is the reciprocal of the poles[5].

    A detailed description of the CF's, PGA's design is presented in Sections 2 and 3 respectively. Section 4 shows the measurement results, and Section 5 is the conclusion of the paper.

2.   Circuit design of CF
  • The class-A FDOPA is common in active-RC CF and PGA. Its maximum output current swing is limited by the bias current of the output stage. This drawback leads to a large standby current and poor linearity. The class-AB FDOPA resolves this problem effectively for its output current is provided by both the PMOS and NMOS transistors of the output stage, even though the bias current is small[6].

    A simplified schematic of the fully differential analog baseband circuit and the CF's ATC are shown in Figures 3 and 4respectively. A detailed description of the circuit design is shown below.

  • 2.1.   CF architecture

  • The CF's pass-band bandwidth of 1.6 MHz centered at 2~MHz is slightly larger than the DAB's channel bandwidth of 1.536 MHz to accommodate frequency offset[12]. A 3rd order Chebyshev-I active LPF prototype of the 800 kHz bandwidth employing a leap-frog structure will meet the requirements of 40 dB image band rejection[7].

    As shown in Figure 3, the transfer function of the LPF prototype is,

    The center frequency of the CF is,

    We find that the bandwidth and center frequency are both inversely proportional to the capacitance of the capacitors when the resistors are fixed. Therefore, the CF's bandwidth and center frequency can be tuned simultaneously by tuning the capacitor banks shown in Figure 4[8]. The tuning scheme will be shown later. The area of the CF is dominated by the capacitors[9]. A smaller capacitor means a larger resistor; therefore, a tradeoff between the die area and noise should be made. As shown in Figure 4, the capacitor bank consists of a fix capacitor $C_{3}$ and 6-binary weighted capacitor array of unit capacitor $C_{2}$. The capacitance of the capacitor bank can be tuned to 64~discrete values by the 6-bit control code,

  • 2.2.   FDOPA

  • A class-AB Miller FDOPA designed for both CF and PGA is shown in Figure 5[10]. The PMOSs, M6 and M7, of the output stage are driven by the outputs of the 1st stage directly, while the NMOSs, M10 and M11, are driven by source followers M8 and M9[6]. The push pull operation of M6, M7, M10 and M11, will provide a large enough current to the feedback resistors and capacitors of the CF and PGA. The circuit does not suffer from the linearity problem caused by the limited output current of the class-A FDOPA. The output stage quiescent current can be described by the equations below,
    $V_{\rm SG6} +V_{\rm GS8} +V_{\rm GS10} =V_{\rm DD}, $(4)
    $I_{\rm sd6} =\frac{\beta _6}{2}\left( {V_{\rm GS6} -V_{\rm THP} } \right)^2=I_{\rm ds10} =\frac{\beta _{10} }{2}\left( {V_{\rm GS10} -V_{\rm THN}} \right)^2, $(5)
    where $V_{\rm GS8}$ is determined by the M17 bias current and the aspect ratio of M8. $\beta$ is the transconductance parameter. So a low quiescent current of the class-AB output stage can be achieved by choosing a proper value of $V_{\rm GS8}$. Simulated results show that the DC gain is 65 dB, the gain-bandwidth product is 310 MHz with a 52$^\circ$ phase margin. The standby current of each FDOPA is 350 $\mu $A. The simulated result shows that the maximum differential output current is 900 $\mu $A.

  • 2.3.   ATC

  • An ATC consisting of an integrator, a comparator and a digital logic circuit controls the capacitor bank with a 6-bit register[8, 9]. To tune the bandwidth and center frequency of the CF is to tune its RC time constant[10]. Figure 6 is the flow chart of the ATC. As shown in Figure 4, $C_{\rm T}$ is a copy of the capacitor bank of the CF and $R_{\rm T}$ is a copy of $R_{4}$. The time constant of the $C_{\rm T}$ and $R_{\rm T}$ is 3.1416 $\mu $s. When the circuit starts to work, the 6-bit control code is reset to 011111. Afterwards, switch S$_{1}$ is off and switch S$_{2}$ is on, so all the residual charge in $C_{\rm T}$ will sink to the ground. Then the digital circuit turns on switch S$_{1}$ and turns off switch S$_{2}$, and $C_{\rm T}$ is charged by the current mirror of MT1 and MT2. MT1 and MT2 have the same aspect ratio, so the charging current is,

    The charging time $T_{\rm char}$ is set to be equal to $T_{\rm cons}$. When switch S$_{1}$ is turned off, the voltage of $V_{\rm comp}$ is,

    So if the time constant of $R_{\rm T}C_{\rm T}$ is larger than $T_{\rm cons}$, it means the capacitance of $C_{\rm T}$ is greater than required and the output of comparator $D_{\rm comp}$ is 1. Then the circuit will subtract 1 from the control code B. Otherwise, $D_{\rm comp}$ is 0 and B will increase by 1. After 32 cycles, the CF gets the control code B.

3.   Circuit design of PGA
  • The desired gain range and OIP3 of the analog baseband circuit are 10-50 dB and $\geqslant$ 15 dBm respectively. The class-AB FDOPA adopted in the PGA has the same structure as the CF's. The transistors' aspect ratio of the output stage is twice that of the CF's, because the PGA's output swing is larger. The 1st stage provides a fine gain setting of 10-15 dB with a 1-dB step size and the next two stages both provide a coarse gain setting of 0-18 dB with a 6-dB step size. An integral part of the PGA is the dc offset cancellation. A small DC offset can be amplified to a level that will clip the output signal. The detailed circuit design is presented below.

  • 3.1.   PGA switch network

  • Figure 7(a) shows the conventional structure of the PGA cell. Assuming that the FDOPA is ideal and taking the switch resistor $R_{\rm SW}$ into account, when switch $S_{\rm f1}$ connects $R_{\rm f1}$ to the negative input of FDOPA, the gain of the PGA cell is,

    Here, $R_{\rm SW}$ impacts the gain of the PGA cell directly. In order to obtain low noise and considering the FDOPA's driving capability, the resistance of $R_{\rm f1}$ and $R_{\rm S}$ is set to 5 k$\Omega $ in this design. Simulated results show that $R_{\rm SW}$ is about 215~$\Omega $. In the worst case, the gain deviation is 20lg(5215/5000) $=$ 0.366 dB. So $R_{\rm SW}$ affects the gain significantly. Smaller $R_{\rm SW}$ means larger transistors and larger parasitic capacitors, so increasing the aspect ratio of the transistors in the switch is not a good method to improve the gain accuracy. A new structure, shown in Figure 7(b), fundamentally eliminates the gain deviation caused by $R_{\rm SW}$. In this structure, $R_{\rm SW}$ become a part of the FDOPA's input impedance, which is almost infinite. No matter how large $R_{\rm SW}$ is, the gain will not be affected. The five resistors in Figure 7(b) function like a digitally controlled potentiometer and the switches function like a potentiometer knob. The gain is determined by all the series resistors on the left of the closed switch and the others on the right. Therefore, it will provide more accurate gain.

  • 3.2.   DCOC

  • A DCOC circuit is necessary in PGA, because the small input dc offset can be amplified to be large enough to decrease the PGA's dynamic range severely[11]. Both digital and analog circuits have been researched to compensate for the dc offset. In this design, a low pass feedback circuit is introduced to make the circuit's dc gain negative. As shown in Figure 3, the lowpass feedback circuit consists of a 1st order $RC$ low pass filter and a voltage buffer. $R_{9}$ is the MOS resistor and $C_{1}$ is the MIM capacitor. Assuming the FDOPA is ideal, the transfer function of the PGA is,
    $H_{\rm PGA} (s)=\frac{A_{2, 3} R_6 }{R_5 } \frac{R_9 C_1 s+1}{(R_9 C_1 s+1)+A_{2, 3} R_6 /R_{10} }.$(9)
    where $A_{2, 3}$ is the gain of the PGA's 2nd and 3rd stage. The DCOC circuit should not affect the gain of the signal band. Equation (9) indicates that at the channel center frequency $f_{0}$,

    Compared to the maximum signal period of about 1 $\mu $s, the time constant of $R_{9}C_{1}$ is very large. So the RC time constant of the DCOC circuit is at the scale of ms. If we adopt integrated resistors and capacitors to get such a large time constant, the area will be too large to integrate. When the MOS transistor works in the cutoff region, the impedance between the drain and the source, $R_{\rm ds}$, is very large. The simulated result shows that the impedance $R_{\rm ds}$ is 300 M$\Omega $. A 10 pF capacitor is enough to realize the time constant. Therefore, it is possible to integrate the DCOC circuit for the small size of the MOS resistor[12, 13].

    Figure 8(a) shows an implementation of MOS resistor. When there is little DC offset, the voltage of the transistor's gate, source and drain are equal, so all the transistors work in the cutoff region. The AC impedance is quite a large resistor. When there is a large DC offset at the output, the transistors will work in the sub-threshold region and the current will charge or discharge $C_{1}$ to cancel the offset. Because of the quite small charging current of the transistors working in the sub-threshold region, the obvious disadvantage of this MOS resistor is the long settling time. When the DC voltage of the outputs approaches $V_{\rm cm}$, the current will be much smaller. To solve this problem, a new MOS resistor is proposed, as shown in Figure 8(b). All the transistors' gates are biased to $V_{\rm cm}$. When the PGA works normally, the transistors also work in the cutoff region, like the transistors in Figure 8(a); when there is a large dc offset, the transistors work in the saturation region or triode region to provide a much larger current than the transistors of the sub-threshold region and cancel the offset quickly. The simulated result shows that the settling time is improved from 100 to 1~ms. $R_{10}$ is half of $R_{5}$, so the DC gain of the PGA $G_{\rm DC}$ is $-6$ dB. The area of the MOS resistors is negligible.

4.   Measurement results
  • The circuit has been fabricated in the SMIC's 0.18-$\mu $m RF CMOS process, as shown in Figure 9. The die area of the core circuit is 780 $\times$ 540 $\mu$m$^{2}$. Figures 10(a) and 10(b) give the amplitude response before and after tuning at the gain of 20 dB respectively. The plot after tuning indicates the ATC has rectified the circuit's pass-band effectively. The gain ripple is less than 0.3 dB. Figure 11 shows the gain and gain accuracy of the circuit at 2 MHz. The minimum gain is 10.01 dB and the maximum gain is 49.77 dB. The gain accuracy of each gain step is within $\pm $0.3 dB. Figure 12 shows that the differential OIP3 of the circuit is 18.3 dBm at the gain of 50 dB, and the OIP3 is up to 23.3 dBm at a 10 dB gain. The differential IP$_{\rm 1dB}$ is 4.7 dBm at a 10 dB gain. Table 1 summarizes the key measurement results and compares it to three other works. The gain accuracy of this circuit has an advantage over the other works. The proposed switch network has provided a precise gain control. The comparison between OIP3 and IP$_{\rm 1dB}$ shows that at the minimum gain setting, this work's linearity is better. The output dc offset is less than 10 mV. The current consumption is 4.5 mA from a 1.8 V supply voltage.

5.   Conclusions
  • In this paper, a highly linear analog baseband circuit with accurate gain control is presented. The frequency response can be tuned accurately by the ATC. To prevent DC offset, a new DCOC circuit based on the MOS resistor has been designed. High gain accuracy ($\pm $0.3 dB) is achieved with a 1 dB gain step from a 10-50 dB voltage gain. This precise gain control benefits from the PGA's novel switch network and the large output current swing of the class-AB FDOPA. This circuit has been integrated in a DAB RF front end.

    Acknowledgement The authors wish to thank Li Wei and Zhang Li for their technical instructions. The authors also gratefully acknowledge the helpful comments and suggestions of the reviewers, which have improved the presentation.

Figure (12)  Table (4) Reference (16) Relative (20)

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