A low power 11-bit 100 MS/s SAR ADC IP

Key words: analog-to-digital converterSARhybrid ADC

Abstract: This paper presents a dual-channel 11-bit 100 MS/s hybrid SAR ADC IP. Each channel adopts flash-SAR architecture for high speed, low power and high linearity. Dynamic comparators in the coarse flash ADC and the fine SAR ADC further contribute to the reduction of power consumption. A gate-controlled ring oscillator generates a multi-phase clock for SAR logic, thereby allowing it to asynchronously trigger the comparator in the fine SAR ADC in high speed. MOM capacitors with a fully shielded structure provide enough matching accuracy without the need for calibration. This design was fabricated in SMIC 55 nm low leakage CMOS technology and the active area of dual-channel (I-Q) ADC is 0.35 mm2, while the core area is 0.046 mm2. It consumes 2.92 mA at a 1.2 V supply, for dual-channel too. The effective number of bits (ENOB) is 9.90 bits at 2.4 MHz input frequency, and 9.34 bits at 50 MHz, leading to a FOM of 18.3 fJ/conversion-step.

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1.   Introduction
  • SAR ADCs are attractive for medium to high resolution applications due to their excellent power efficiency. Since an N-bit SAR ADC with traditional structure requires $N$ comparisons to complete one conversion, and the speed of each comparison is limited by the DAC setting time and control loop delay, it is a great challenge to design a SAR ADC with high resolution for a high bandwidth wireless communication system.

    Some hybrid architectures, such as pipeline-SAR[1] and flash-SAR[2], have been proposed to improve conversion speed and optimize power consumption. The key building blocks, mainly comparator, SAR logic and capacitive DAC (CDAC), have also been intensively researched for better performance[3, 4]. Low offset dynamic comparators[5], the energy-saving switching sequence technique[6] and C2C DAC[7] are proposed for a better power efficiency than conventional structures.

    In this work, we explore the design of a coarse flash ADC combined with a fine SAR ADC without a sample and hold amplifier (SHA) to increase speed and reduce power consumption. We also optimized the DAC setting time and logic delay with asynchronous timing. A faster and lower complexity switching method has been used in this design.

    The rest of this paper is organized as follows. Section 2 describes the architecture and timing of this work. Section 3 details the consideration of faster SAR logic, switching method and asynchronous clock generator for high speed. Section 4 gives the methods to reach 11-bit resolution and focuses on layout design. In Section 5, the measurement results are presented. Finally, conclusions are drawn in Section 6.

2.   ADC architecture
  • Figure 1 shows the block diagram of the reported ADC IP. It consists of a 3.5-bit flash ADC for coarse conversion and an 8-bit SAR ADC for fine conversion. The fine SAR ADC includes a CDAC, a comparator and SAR logic. Both the coarse flash ADC and the fine SAR ADC adopt dynamic comparators for low power. The flash ADC and CDAC acquire the input via bottom plate sampling through the bootstrap switches, which can avoid kickback noise and maintain linear input. At the end of the sample phase, the input voltage is sampled on the CDAC, and the coarse flash ADC begins to convert the input voltage at this instant. The flash ADC performs the first 3.5-bit conversion and determines the sub range where the input signal is located, so the residue voltage for the subsequent SAR ADC becomes smaller. It can avoid the unnecessary capacitor charging and discharging from reference voltages compared with the traditional SAR, which means it consumes lower power. This structure can also obviously increase the operation speed.

    A SHA-less technique is used to reduce the power consumption, too. Figure 2 shows the sample network of flash and SAR. Both of the inputs are sampled via bootstrap switches. As shown in Figure 2(a), the reference voltage is stored on the capacitor when the SAR is converted. Then, the actual input of the comparator in flash is the difference between the input voltage at the raised edge of the K2ND and its reference voltage. Figure 2(b) shows the sample network of SAR, which is a split-CDAC. The input voltage is stored on the comparator at the falling edge of K2B. The RC matching between the two networks is already concerned when the circuit is designed. So the aperture error is mainly determined by $\Delta t$ shown in Figure 2(c). Since there 0.5 bit resolution redundancy in this design, $\pm $$\frac{1}{32}$ full scale range offset or error can be tolerated[2]. The aperture error between different sample networks of flash and SAR could be self-calibrated because of this redundancy.

    This design has better power efficiency than other flash-SAR architectures[2] because the SHA-less technique and dynamic comparators are used to reduce the power consumption further. Besides, a multi-phase clock generator is presented in this design.

3.   High speed consideration
  • A conventional 11-bit resolution SAR ADC needs 11 comparisons to complete one conversion. This means each comparison has less than 455 ps (assume the clock's duty ratio is 50 %), if we consider the non-overlap time loss, the time will be a little shorter. The flash-SAR architecture described in Section 2 can reduce the eleven comparisons to nine comparisons (eight for SAR, one for flash), thus a higher speed is achieved. In this section, we focus on improving the speed of one comparison in the fine SAR ADC. The speed of one comparison is limited by the sum of the DAC setting time, the comparator decision time and the SAR logic delay. A two-stage dynamic comparator is used in this design to reduce the comparator decision time.

  • 3.1.   SAR logic and DAC setting

  • The SAR logic in a SAR ADC has the following two functions. (i) Store the comparator decision until the next conversion cycle. (ii) Generate the control signals of the switches for the bottom plate of capacitors in CDAC as soon as possible.

    Figure 3 shows the schematic of the dynamic latch in SAR logic in this design. The switch controlled signal SC<$i$> ($i=$ 7-0) is generated by the control logic, which just enables the corresponding latch in the (8$-i$)-th comparison. The outputs of latch LO{\_}N<$i$>/LO<$i$> control the switches of the bottom plate through an inverter immediately, as shown in Figure 4, so the speed of SAR logic is quicker. The positive feedback network is added to reduce the leakage effect.

    When doing input sampling and MSB conversion, the bottom plates of LSB keep connecting to negative reference voltage (VRN). This can avoid the situation of connecting to common mode voltage (VCM), which should be very slow due to high on-resistance under low overdrive voltage. It results in an input common mode voltage of comparator fluctuation less than 1~mV through a complete conversion, which does not affect the accuracy. Similarly, the MSB capacitor turns into two halves (as shown in Figure 2(b)), alternatively one connected to VRN and the other connected to positive reference voltage (VRP), to instead the situation connected to VCM.

  • 3.2.   Asynchronous clock generator

  • The asynchronous SAR logic needs a high-speed multi-phase clock to trigger the comparator. The period of the asynchronous clock must adapt to the sum of DAC setting time, comparator decision time and SAR logic delay so that the CDAC can settle to enough accuracy before the next comparison. Since the SAR logic delay and DAC setting time are optimized for high conversion speed, the generated multi-phase clock must be fast enough. Therefore, it is a great challenge to generate a suitable internal clock.

    The multi-phase clock generator is illustrated in Figure 5. A gate-controlled ring oscillator (GCRO) is designed to generate a multi-phase clock. The oscillation is controlled by GT. When GT $=$ 0, the output of NAND maintains high, so that the GCRO remains static. When GT $=$ 1, the GCRO starts oscillating, and the period of oscillation is determined by the decision and reset time of the comparator, and the delay time of NAND and NOT gate. This is indicated in Equation (1):
    \begin{split} T_{\rm CKC} ={}& T_{\rm com, decision} +T_{\rm NAND, up} +2T_{\rm H} \\[2mm]& +T_{\rm com, reset} +T_{\rm NAND, down}, \\ \end{split} (1)
    where $T_{\rm com, decision}$, $T_{\rm com, reset}$ are the decision and reset time of the comparator, $T_{\rm NAND, up}$, $T_{\rm NAND, down}$ are the delay of pull up and pull down of NAND, and $T_{\rm H}$ is the delay of the inverted delay unit. As described above,
    $ T_{\rm CKC} \geqslant T_{\rm com, decision} +T_{\rm logic} +T_{\rm setting} , $(2)
    where $T_{\rm logic}$ is the delay of SAR logic, and $T_{\rm setting}$ is the time for CDAC setting to the required accuracy. Then,
    \begin{split} {}& T_{\rm com, reset} +T_{\rm NAND, up} +2T_{\rm H} +T_{\rm NAND, down} \\[2mm]& \geqslant T_{\rm logic} +T_{\rm setting}. \\ \end{split} (3)
    Based on the above analysis, we can resize the NAND and inverted delay unit to adjust the period of the generated clock. In this work, the inverted delay unit contains three inverters with different sizes.

4.   Accuracy consideration

    4.1.   Offset of dynamic comparator

  • The schematic of the dynamic comparator in the coarse flash is shown in Figure 6. Since nominally-identical devices suffer from a finite matching accuracy due to uncertainties in each step of the manufacturing process, the circuit is not perfectly symmetric. It may lead to DC offset in symmetric circuits, which should cause comparison mistakes. This architecture tolerates the offset of a coarse comparator up to $\pm $$\frac{1}{32}$ of the full scale range. Hence, the matching requirement of the flash comparator greatly relaxes.

    According to the Monte Carlo simulation results, the offset of this comparator is mainly decided by the gate area of input devices M1 and M2. So we increase the $WL$ while $W/L$ maintains constant to meet the offset requirement. This will somehow slow down the speed of comparator decision. Since the comparator of the coarse flash ADC is just used in the first comparison, it does not have much impact on speed.

  • 4.2.   Noise

  • The main noise source of this design is the comparator of the fine SAR ADC. We also use the structure shown in Figure 6 in the SAR for its perfect power consumption and speed. In the first step of circuit design, we do sizing of each MOS device to optimize speed. The noise power of this circuit is inversely proportional to the load capacitance of nodes P, N. So in the second step, we increase the size of each MOS device proportionately to meet the noise requirement. Since the whole device expands proportionately, the speed of this comparator almost maintains constant.

  • 4.3.   Matching

  • As described in Section 4.1, the uncertainties in each step of the manufacturing process lead to nominally-identical devices. The capacitor mismatch causes A/D conversion nonlinearities. To achieve 11-bit accuracy without the assistance of digital calibration, the unit capacitor is evaluated to 20 fF to satisfy the matching requirement.

    The matching accuracy is also determined by the layout. Since the top plates of the capacitor in CDAC are sensitive to parasitic capacitances, the top plate is totally surrounded by the bottom plate to reduce parasitic capacitances and interference, as shown in Figure 8. These MOM capacitors with their fully shielded structure provide enough matching accuracy.

5.   Measurement results
  • This design was fabricated in SMIC 55 nm low leakage CMOS technology and has been tested. This technology is determined by the SOC. Low leakage technology has a thicker gate oxide than the general purpose technology; therefore, it has higher threshold voltage and lower leakage current. This leakage optimization can reduce the static power consumption of digital circuits in SOC. The active area of this design is 500 $\times$ 700 $\mu $m$^{2}$ for the dual-channel (I-Q) and the core area is 0.046~mm$^{2}$. The photomicrograph of the ADC IP is shown in Figure 8.

    A printed circuit board (PCB) is designed and fabricated to test this design. The supply voltage is generated by a low dropout regulator (LDO). Besides, the input signal is different frequencies of single-tone sine and the digital outputs are stored by a data acquisition board. Harmonic analysis by fast Fourier transform (FFT) could calculate the dynamic parameters of the ADC. The static performance is measured by a code density test with a full swing sinusoidal input.

    Figure 9 shows the static performance measured using a code density test with a full swimming 2.4 MHz sinusoidal input. The output spectra at 2.4 and 50 MHz input frequency are shown in Figures 10 and Figures 11. At a sampling rate of 100.11 MS/s, the ADC can achieve an ENOB of 9.90 @ 2.42 MHz and 9.34 @ 50 MHz. Dynamic performances are depicted in Figure 12. Since this design is an IP for wireless communication SOC, the power consumption could not be measured alone. According to the post layout simulation results, it consumes 3.51 mW for the dual-channel when all the parasitic resistances and capacitances in the layout are concerned. A common FOM is used to compare the performance, which is given as

    The FOM of the ADC is an 18.3 fJ/conversion-step using Equation (4). Table 1 shows the performance summary and results compared with some low-power designs. According to Table 1, this design achieves a better power efficiency than other similar ADCs and has a smaller core area.

6.   Conclusions
  • A dual-channel 11-bit 100 MS/s SAR ADC IP, which was fabricated in SMIC 55 nm 1P8M low leakage CMOS technology, has been presented in this paper. Each channel adopts flash-SAR architecture for high speed, low power and high linearity. The SHA-less technique is also used to reduce the power consumption. Measured results achieve an ENOB of 9.90 at 100.11 MS/s, leading to a FOM of an 18.3 fJ/conversion-step.

Figure (12)  Table (4) Reference (9) Relative (20)

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