Resistive random access memory and its applications in storage and nonvolatile logic

    Corresponding author: Lifeng Liu,
    Corresponding author: Xing Zhang,
  • Institute of Microelectronics, Peking University, Beijing 100871, China

Key words: RRAMmemorynonvolatile logicmetal-oxideresistive switching

Abstract: The resistive random access memory (RRAM) device has been widely studied due to its excellent memory characteristics and great application potential in different fields. In this paper, resistive switching materials, switching mechanism, and memory characteristics of RRAM are discussed. Recent research progress of RRAM in high-density storage and nonvolatile logic application are addressed. Technological trends are also discussed.


1.   Introduction
  • CMOS scaling is approaching its physical limits, it is hard to meet the needs of storing and processing the ever growing information. New memory and computation devices with great scalability, high speed and low power consumption are desired. For the new memory device, a so called storage class memory (SCM) with high density, high speed and non-volatility is highly demanded to fill the gap between existing DRAM and NAND flash [1]. A nonvolatile logic device with low energy dissipation is under development as it is one of the promising technologies to break the von Neumann bottleneck in conventional computing systems [3-5]. It is notable that the nonvolatile memory devices have been demonstrated to perform the nonvolatile reconfigurable logic operation [5-7].

    Charge storage based flash memory is widely used in consumer electronic products. However, flash memories suffer from a charge loss problem and approach the integration limit as the feature size of the device continues to shrink [8, 9]. Emerging memories to replace conventional flash memories have been extensively studied as potential alternatives to existing memories in future information systems. Novel nonvolatile memory technologies such as magnetic random-access memory (MRAM), spin-transfer torque random-access memory (STT-RAM), phase-change memory (PCM), and resistive random-access memory (RRAM) combine high speed, high density and non-volatility and are attracting a great deal of attention [9-14]. In the new memories, the data is stored as a configuration of atoms/ionic defects or electronic spin instead of as electronic charge. The MRAM cell is typically based on the M/I/M (magnetic metal/insulator/magnetic metal) structure having two magnetic elements, one with a fixed magnetic polarity and another with a switchable polarity. The MRAM cell shows high operation speed and long endurance [15]. STT-RAM is a new kind of MRAM which has good scalability and fast access time [16]. PCRAM is a type of nonvolatile memory device based on a phase change of the active material from a high resistive amorphous phase to a conducting crystalline phase. PCRAM cells have the advantages of fast switching speed, multi-level operation and good scalability [17].

    RRAM has been under extensively study as one of the promising candidates for the storage class memory application, for its outstanding performance such as fast write speed, low power consumption, great scalability, three-dimensional integration, low cost and is compatible with the CMOS fabrication process [18-20]. Resistive switching operation of RRAM is based on the resistive switching phenomena in simple metal-insulator-metal structure. In this paper, we will briefly introduce the resistive switching materials and switching mechanism. We will also address the development of RRAM in nonvolatile memory and discuss the main challenges especially on the selector device for the application in crossbar arrays. Then, a nonvolatile logic application of the resistive switching device is also discussed. Finally, we conclude this paper with an outlook for RRAM.

2.   Resistive switching materials and mechanism

    2.1.   Resistive switching materials

  • The phenomenon of resistance change in some insulators under an electric field has been demonstrated a long time ago, which dates back to 1962 [21], however, it did not attract much attention until the 1990s. The conception of resistive switching (RS) was proposed in 1997 [22] and people began to study how to apply it into a memory device [23]. Soon more and more materials were found to exhibit the resistive switching behavior, which are mostly oxide materials including complex metal oxides such as the pervoskite oxide of SrTiO $_3$ [24] and the binary metal oxides such as HfO $_{x}$ [25, 26], TiO $_{x}$ [27, 28], NiO $_{x}$ [29], ZrO $_{x}$ [30, 31], TaO $_{x}$ [32, 33], ZnO $_{x}$ [34], and AlO $_{x}$ [35]. Among these resistive switching materials, binary metal oxide is the most promising for practical applications due to its compatibility with CMOS BEOL processing. In addition, resistive switching characteristics have been demonstrated in some organic materials, such as poly (methylmethacrylate) (PMMA) [36]. Organic resistive switching materials have attracted considerable attention due to their easy fabrication, low cost, and high mechanical flexibility for future flexible device applications.

    The RRAM device usually has a stacked structure of metal/resistive switching layer/metal. A resistive switching layer is sandwiched between the top and bottom electrode, as shown in Fig. 1. The bottom electrode material is usually Pt, which is hard to etch. For single devices, they can share the same bottom electrode. However, for the crossbar architecture, the bottom electrodes of each device are separate. They can be obtained by lithography, physical vapor deposition (PVD) and lift-off successively. Resistive layer and top electrode material are usually metal oxides and TiN, grown with atomic layer deposition (ALD) or PVD, which are easy to etch after lithography.

    Electrode materials play an important role in the resistive switching characteristics. The activity of the electrode material, work function, and the interface between the electrode and the resistive switching layer will affect the resistive switching behaviors [14, 18]. When an active and diffusive metal like Ag [37-39] or Cu [40, 42] is used as electrode materials, the RRAM device is usually regarded as a conductive-bridge based RRAM (CBRAM), in which diffusive metal atoms are easy to transport in the solid electrolyte and form the conductive bridge.

  • 2.2.   Resistive switching mechanism

  • The resistive switching process from a high resistance state (HRS) to a low resistance state (LRS) is called the "set" process, while switching from LRS to HRS is the "reset" process. The fresh RRAM devices usually show an initial high resistance state. A high voltage electroforming process is always needed to switch the fresh devices to a low resistance state [43]. The resistive switching of RRAM can be classified into two types: unipolar type and bipolar type. Figs. 2(a) and 2(b) show a schematic of the $I$ - $V$ characteristics for the unipolar and the bipolar switching, respectively. In the unipolar switching, the resistive switching depends on the applied voltage amplitude and not on the applied voltage polarity. The set/reset process can occur at the same polarity. In the bipolar switching, the resistive switching depends on the applied voltage polarity. The set process can only occur at one polarity and the reset process can only occur at the reverse polarity.

    The physical mechanisms of resistive switching behavior have been the hot topic in RRAM research. Though some details in the RS process are under dispute, the most widely accepted resistive switching mechanism of the metal-oxide based RRAM is the formation and rupture of conductive filaments (CFs) in the oxide layer [43-46]. However, the proposed physical origin of CFs is very diverse, including thermal effect [47], ionic conduction [48], electronic effect [49], metal-insulator transition [50] and ferroelectricity [51]. A unified resistive switching mechanism and the related physical model and analytical model of metal-oxide RRAM was proposed and established to explain the resistive switching effect and guide the optimization design of metal-oxide based RRAM devices [52-57]. Fig. 3 schematically illustrates the resistive switching process of set and reset in oxide based RRAM devices. The bottom electrode (BE) is always grounded. In the set process, positive bias is applied on the top electrode (TE). Oxygen vacancies (V $_{\mathrm{O}}^{\mathrm{2+}})$ are generated in the metal oxide under the electric field, while the oxygen ions (O $^{\mathrm{2-}})$ drift to the TE where these oxygen ions are discharged into neutral non-lattice oxygen or reserved in the TE metal under the electric field. More and more oxygen vacancies accumulate to form CFs connecting the BE to the TE and electrons can hop between these oxygen vacancies. Thus, a metal-oxide based RRAM device is in LRS after the set process. Inversely in the reset process, a negative bias is applied on the TE. Oxygen ions previously reserved in the TE are released and drift to the metal oxide layer under a reverse electric field, where they can recombine with the oxygen vacancies, causing the rupture of CFs and the metal-oxide based RRAM device returns to the HRS. A unified microscopic principle is proposed to clarify the unipolar and bipolar switching characteristics of metal-oxide based RRAM [53]. The resistive switching type is correlated with the distribution of localized oxygen vacancies in the metal oxide switching layer, which is determined by the generation and recombination with dissociative oxygen ions. However, there is still some debate on the mechanism of the metal-oxide based RRAM. For example, where the CF starts to grow in the set process and where to break in the reset process, and how these oxygen vacancies gather to form the CFs [58, 59].

    In CBRAM, the formation and rupture of the conductive bridge depends on reactive metal atoms [60, 61]. As is shown in Fig. 4, in the set process, a positive bias is applied on the TE. The reactive TE metal atoms are oxidized to metal ions and drift to the BE through the solid electrolyte. When reaching the BE, metal ions receive the electrons and reduce to metal atoms and accumulate until the conductive bridge is formed and the CBRAM turns into LRS. In the reset process, a negative bias is applied on the TE. The conductive bridge metal atoms usually near the BE get oxidized into ions and drift back to the TE under the electric field, causing the rupture of the conductive bridge and returning the CBRAM device to HRS. Some issues need to be clarified in CBRAM, such as the microscopic process and distribution control of ion migration.

    To fully understand the mechanism of resistive switching in RRAM devices, many research groups have tried to directly observe the behaviors of CFs in RRAM devices during the set and reset process. It is hard to directly observe the CFs of a metal-oxide RRAM that is made of oxygen vacancies. Many research groups are using the indirect method to observe the CFs of oxide RRAM devices. Son et al. of the Pohang University of Science and Technology observed the formation and removal of a filament in the RRAM of Hg/NiO/Pt with a conducting atomic force microscope (C-AFM) [62]. IMEC also drew the current map of TiN/HfO $_{\mathrm{2}}$ /Hf/TiN in the LRS and HRS using C-AFM [63, 64]. Samsung Electronics observed the CFs in the Pt/SiO $_{\mathrm{2}}$ / Ta $_{\mathrm{2}}$ O $_{{5-x}}$ /TaO $_{{2-x}}$ /Pt structure with high-resolution transmission electron microscopy (HRTEM) [65]. The Institute of Physics of the Chinese Academy of Sciences fabricated a Nb/ZnO/Pt RRAM device and measured the local current with different voltages to indirectly observe the CFs in the device using C-AFM [66]. They also directly observed the CFs in the resistive switching process, to some extent, from the distribution of oxygen in HfO $_{\mathrm{2}}$ by using TEM with electron holography, in-situ low-energy-filtered imaging, and in-situ electrical characteristic measurements, as shown in Fig. 5 [67].

    In the CBRAM devices, the CFs are made of metal atoms, which are easier to observe. Researchers at the University of California observed the CFs of Cu in Pt/Al $_{\mathrm{2}}$ O $_{\mathrm{3}}$ /Cu CBRAM devices with in-situ TEM [60]. Yang et al. [68] have directly observed the Ag CF dynamics in different electrolytes and found that CF growth can be limited by the cation transport process. The important role of the dielectric/inert-electrode interface was also highlighted. This work not only broadens the understanding of the switching mechanism in CBRAM but also provides the guidance of device and material optimization. IMEC has comprehensively researched the mechanism of resistive switching of TiN/Al $_{\mathrm{2}}$ O $_{\mathrm{3}}$ /Cu/Au with C-AFM [69, 70]. The Institute of Microelectronics of the Chinese Academy of Sciences performed real-time characterizations of the CF formation and rupture process using TEM in the Ag (or Cu)/ZrO $_{\mathrm{2}}$ /Pt RRAM device [61], and they directly observed the CFs in the Ag/SiO $_{\mathrm{2}}$ /Pt device using SEM and TEM, which is shown in Fig. 6 [71].

  • 2.3.   Resistive switching characteristics

  • Table 1 compares metal-oxide based RRAM with CBRAM from aspects such as speed, voltage, current and so on. Both metal-oxide based RRAM and CBRAM can reach very fast switching speed and low operation voltage. The most distinguished difference between the two RRAMs is the endurance characteristic. CFs of CBRAM are made of metal atoms, which are much easier to drift and diffuse than the oxygen vacancies, causing the endurance cycles and retention time of CBRAM to be worse than the metal-oxide based RRAM. What needs to be pointed out is that these RS characteristics are not obtained in the same device, thus, tradeoffs between these characteristics are necessary when designing RRAM devices.

3.   Nonvolatile memory and storage
  • For the non-volatility, low power consumption, multi-level resistance states, and 3D integration potential, the RRAM device firstly is conceived to be applied in nonvolatile high-density memory technology. Different kinds of RRAM technologies have been developed from multi-level storage to 3D crossbar architecture.

  • 3.1.   Multi-level resistive switching

  • Multi-level storage is an efficient way to achieve ultra-high storage density. There are different methods to realize multi-level resistive switching [7]. It can be realized by coupling two or more independent switching mechanisms into one RRAM cell, such as a Cu/TaO $_{x}$ /Pt structure [80]. However, the coupled switching mechanism is complicated and the multi-level switching is not easily achieved. Multi-level switching can be realized by carefully controlling the resistive switching process of a RRAM cell. Fig. 7 shows the multi-level resistive switching operation under DC test mode and the good uniformity of multi-level states [81]. With different current compliance, the shape and number of CFs is different. In the set process, with increasing the current compliance, the CF gets thicker and more CFs appear and LRS becomes lower. Similarly, in the reset process, as the reset voltage increased, the gap region from CFs to the electrode caused by the CF rupture gets larger, and a higher HRS can be realized.

    Fig. 8 shows the multi-level operation of a Pt/W/TaO $_{x}$ /Pt RRAM cell [82]. The multi-level resistive switching of the W-electrode TaO $_{x}$ RRAM has been examined with various reset stop voltages. By performing a higher deep-reset switching process, W-electrode TaO $_x$ RRAM can show a high resistance ratio (>10 $^{\mathrm{3}})$ . The 3-bit multi-level cell (MLC) characteristics are realized in the W-electrode TaO $_{x}$ RRAM device. An excellent retention for these eight states is demonstrated at 125 ℃ for 10 $^{\mathrm{4 }}$ s.

    Multi-level operation also can be realized by taking advantage of the conductance quantization phenomenon, such as a Ag/Ta $_{\mathrm{2}}$ O $_{\mathrm{5}}$ /Pt structure [83]. Realizing multi-level resistive switching by the use of conductance quantization is very promising as the increase of controllability and clear understanding of kinetics of conductance quantization.

  • 3.2.   Crossbar array and selector

  • The crossbar array has a very important architecture for practical use of RRAM due to its ultra-high density integration. Fig. 9(a) shows the schematic of the crossbar RRAM array. The RRAM array faces the severe sneak path problem, which is shown in Fig. 9(b). Typically, the resistive switching memory cell is sandwiched by two sets of parallel electrodes as word lines (WL) and bit lines (BL). The switching between LRS and HRS occurs when proper voltage is applied between WL and BL. When an RRAM cell is selected, we apply voltage $V_{\mathrm{dd }}$ to the corresponding WL and BL is grounded. If the selected cell is in HRS and other cells around it are all in LRS, in the read operation, the current is much higher than expected. To mitigate these problems, connecting a select device in series to the memory cell is proposed. Select devices have three candidates: transistors, diodes and selectors [84]. Connecting a transistor in series to the RRAM cell, which results in the 1T1R structure, can perfectly suppress the sneak path current. However, due to the complicated process of integrating a transistor array to the RRAM crossbar array, the 1T1R structure has difficulties in improving the density of the array and controlling the cost, though it may have the best performance. Both of the other two devices, diodes and selectors, are to introduce high nonlinear $I$ - $V$ characteristics to the memory cells to suppress the sneak path current. Moreover, they both have simple structure, which can be stacked up to the memory cell directly, which granted them great potentials for high-density integration. Nevertheless, due to the unidirectional feature, diodes, resulting in 1D1R structure, are only compatible with unipolar RRAM. For the more preferable bipolar resistive devices, bipolar nonlinear selectors are needed, resulting in 1S1R structure.

    The selectors are connected in series to the memory cells at the cross points of WL and BL. For the reading operation, there are mainly three schemes: the ground scheme, the $V/2$ scheme and the $V/3$ scheme [85]. In the ground scheme, the unchosen word lines and all the bit lines are grounded. In the $V/2$ scheme, all of the unselected word lines and bit lines are biased at half the read voltage. In the $V/3$ scheme, the unselected word lines biased at one third of the read voltage and the unselected bit lines are biased at two thirds of the read voltage. Different reading schemes result in different array performance and power consumption. Fig. 10 shows a numerical simulation of the read schemes in 1S1R array [85]. The selectivity of the selector device ( $k$ ) is variously defined as the ratio of the current at the full read voltage ( $V$ ) to that at either half-or one-third read voltage ( $V/2$ or $V/3$ , respectively). The sensing margin is defined by the ratio of the values of $I_{\rm sensing}$ or the HRS and LRS of a selected cell normalized by the on-off ratio of the RRAM device. $I_{\rm sensing}$ refers to the current through the memory cell with the read voltage. It can be found that the 1S1R array with higher selectivity can achieve better performance and power consumption, indicating the important role of selectors in optimizing the RRAM crossbar array. Besides, the ground scheme has the highest sensing margin with the largest power consumption. For the balance, $V/2$ schemes or $V/3$ schemes are often used in the 1S1R array.

    An ideal selector should have the following features: high selectivity, high nonlinearity of the $I$ - $V$ curve, low variations, high driving current and low off-state current, robust endurance, low turn-on voltage to avoid failure of the device, and be easily compatible with the CMOS process. Recently, selectors based on various mechanisms have been investigated, including insulator-metal transition (IMT) [86], ovonic threshold switching (OTS) [87], mixed ionic electronic conduction (MIEC) [88], tunnel barrier (TB) [89], field-assisted super-linear threshold selector (FAST) [90] and Schottky barriers [91].

    Selectors based on insulator-metal transition (IMT) can switch between a low resistive metallic state and high resistive insulating state, which is controlled by voltage or temperature. IMT is already observed in transition metal oxide such as VO $_{\mathrm{2}}$ , NbO $_{\mathrm{2}}$ [92, 93]. The current studied IMT selectors, using VO $_{\mathrm{2}}$ and NbO $_{\mathrm{2 }}$ show excellent switching uniformity within 1000 cycles. However, an IMT based selector has a large sneak current, which is determined by the low band gap in the IMT materials.

    Ovonic threshold switching (OTS) behavior was firstly observed in various chalcogenide alloys. Selectors based on OTS often have large selectivity and high on-state drive current, which is explained by different theories including thermally induced electronic switching, impact ionization and recombination, etc.

    Mixed ionic-electron conduction (MIEC) occurs in materials that conduct both electronic charges and ions. Selectors based on MIEC are often Cu-based, combining the movement of Cu ions and electrons to achieve highly nonlinear $I$ - $V$ characteristics. The Cu-based selectors have a desirable low leakage current, while the Cu accumulation failure could be a challenging problem [94].

    Selectors based on the tunneling effect induce an oxide layer as the tunneling barrier to achieve highly nonlinear $I$ - $V$ characteristics by the quantum-mechanical process. These selectors are reported to have very low sneak current and desirable turn-on drive current. Besides, these selectors can be fabricated in the CMOS compatible process.

    Field assisted super-linear threshold (FAST) selectors achieve high selectivity by a super-linear threshold layer (STL), a conducting path which is formed under threshold voltage and disappear under hold voltage. The FAST selectors show a large selectivity with excellent leakage current. Although it shows some desirable features, its actual material system is still unknown.

    The available array size is mainly determined by an acceptable read margin, the on/off ratio of selectors, and the leakage current through the cells. From the chart we can see the majority of them have achieved a high selectivity over 10 $^{\mathrm{4}}$ , while the satisfying on/off ratio should be higher than 10 $^{\mathrm{6}}$ for ultra-dense integration. As for the on-state drive current, selectors should have current density of 10 MA/cm $^{\mathrm{2}}$ , targeting memory cell of 100 nm $^{\mathrm{2}}$ to achieve 10 A switching current, which only two types of selector meet the requirement in the chart. As for the sneak current, it strongly affects the read margin and power consumption of the entire array, which needs to be controlled as low as possible. Most of the selectors have controlled it below 10 $^{\mathrm{-8 }}$ A.

    Though the selectors listed above may acquire some desirable features, none of them meets all the requirements listed above. An omnipotent selector is still waiting for us to discover it. What is more, to guarantee acceptable RRAM array performance, selectors should also have excellent reliability as well as fast switching time ( $<50$ ns). Moreover, a promising selector should also be compatible with 3D-stackable integration and the CMOS process, which means the processing temperature should be lower than 400 ℃ and the preferable operating temperature should be lower than 85 ℃.

  • 3.3.   Three-dimensional (3D) RRAM arrays

  • To achieve ultra-high density storage, many research groups around the world are devoting much energy into RRAM 3D array research [102]. High-density RRAM storage comparable to NAND flash can be achieved by 3D architectures. Horizontal 3D and vertical 3D RRAM array structures were explored to get high-density storage. In horizontal 3D RRAM array structures, multiple 2D RRAM arrays are stacked in a multilayer structure. Six layers horizontal stackable crossbar arrays have been demonstrated [103]. In vertical 3D RRAM array structures, the RRAM cell is formed at the intersection between a vertical metal electrode and a horizontal metal electrode. Compared with horizontal 3D RRAM array structures, vertical 3D RRAM array structures need fewer critical masks in the fabrication process. Vertical 3D RRAM array structure is regarded as the most suitable option for achieving ultra-high memory density [104].

    Research groups of Stanford University and Peking University jointly proposed and fabricated 3D HfO $_{x}$ -based vertical RRAM arrays with great characteristics, and proposed a read/write scheme without disturbing unselected cells [105-107]. Fig. 11 shows the schematic of the 3D HfO $_{x}$ -based vertical RRAM arrays [107]. The vertical resistive switching layers are formed at the intersections of each metal plane electrode and each metal pillar electrode. With the appropriate bias read/write schemes on the word line (WL), bit line (BL) and select line (SL), each RRAM cell in the vertical 3D architecture can be individually accessed. They studied location dependent issues in 3D vertical RRAM arrays based on single-device measurements and array simulation, and compared different 3D RRAM arrays including horizontal stacked RRAM and 3D vertical RRAM using full-size SPICE circuit models. A four-layer HfO $_{x}$ -based 3D vertical RRAM array was fabricated, showing good layer to layer resistive switching variation [108].

    Researchers of the Institute of Microelectronics of the Chinese Academy of Sciences proposed a novel approach to fabricating a 3D vertical RRAM array [109-111]. Fig. 12 shows the 3D architecture, TEM images and its characteristics [111]. In the vertical RRAM array, a four-layer 3D vertical array of TiN/HfO $_{\mathrm{2}}$ /CuGeS/W architecture is fabricated. The RRAM cells in different layers were shown to display similar resistive switching characteristics. They demonstrated a 3D vertical RRAM array with self-selective cell and successfully suppressed the inter-layer leakage, which is helpful for scaling down. The self-selective vertical RRAM cell has excellent characteristics, including low half-select leakage ( < 0.1 pA), high nonlinearity (>10 $^{\mathrm{3}})$ , low operation current (nA level), high endurance (>10 $^{\mathrm{7}})$ , and robust read/write disturbance immunity.

    Research group of the Arizona State University studied the effect of RRAM device characteristics on 3D RRAM array by simulation [112-115]. A SPICE model was established to simulate different 3D crossbar architectures including the horizontally stacked and the vertically stacked structure with different materials to guide the design of 3D RRAM arrays. Design trade-offs of 3D vertical RRAM array were analyzed. A quasi-analytical model was developed to improve the simulation efficiency, overcoming the challenge of MB-level array design. Researchers of the University of California Santa Barbara reported a horizontally stacked array, of which the resistive transition is very smooth during the set and reset process, which is suitable for analog and neuromorphic computing [116]. The Tsinghua University fabricated two different 3D RRAM arrays using graphene and carbon nanotube (CNT) as the edge electrodes. Due to the interface effect, the built-in selector is achieved [117]. They also demonstrated 2-bit resistive switching in 3D vertical RRAM array with the HRS/LRS ratio > 1000, and endurance cycles > 1010 [118]. Although much progress in 3D RRAM has been made, there are still some problems to be addressed, such as selector integration with 3D structure, layer to layer uniformity, and reliability of RRAM cells.

4.   Nonvolatile logic and computing
  • Because of the nonvolatile resistive switching and nonlinear dynamic nature of RRAM devices, reconfigurable logic, and implication logic operations can be executed. Thus, computing and memory functions can be unified with the resistive switching devices, which may pave the way for breaking the bottleneck of conventional computing systems. Much effort has been devoted to applying RRAM to the logic computing technology, by achieving memory and logic operation in the same nonvolatile device [119-124]. The logic in memory architecture may help mitigate the von Neumann bottleneck that will soon come up due to the always fast-growing information and data in the modern society.

    Fig. 13 shows how RRAM is applied in nonvolatile logic computing technology. Fig. 13(a) shows the RRAM array architecture of achieving NOT logic. A and Y are RRAM devices. The resistance value of r is much lower than HRS and much higher than LRS of the RRAM device. The resistance state of A stands for the input and Y stands for the output, in which HRS stands for "0" and LRS stands for "1". The pulse operation to achieve NOT logic is shown in Fig. 13(b). The initial state of Y is HRS. The pulse amplitude applied on V1 is 1 V, if A is in LRS, according to the Kirchhoff laws, most of the voltage is applied on r and the potential of BL is about 1 V. While the pulse amplitude applied on V2 is about 2V and the actual voltage applied on Y is about 1 V, which is below the RRAM set voltage and Y remains HRS. If A is in HRS, according to the Kirchhoff laws, most of the voltage applied on A and BL is almost grounded. While the pulse amplitude applied on V2 is about 2 V and the voltage applied on Y is about 2 V, which is sufficient to set Y to LRS, just as Fig. 13(c) shows. Similarly, the logic of AND, OR can also be achieved with similar RRAM array architectures.

    Implication logic in resistive switching devices was first proposed in 2008. 'Stateful' logic operations were experimentally demonstrated in a row of resistive switching devices via material implication in 2010 [3]. In 'stateful' logic operations performed by RRAM devices, resistance instead of voltage or charge is used as the physical state variable. Rosezin et al. of RWTH Aachen of Germany [125, 126] demonstrated that the IMP function can be realized in a single bipolar RRAM device or a single complemental resistive switching device. They proposed a temporal logic architecture based on bipolar RRAM devices or complementary RRAM and achieved the basic Boolean logic operation and in-memory-adders in the 1 $×$ 8 Pt/HfO $_{\mathrm{2}}$ /Hf/Pt array [127, 128]. Stanford University reported they have achieved NAND logic, NOR logic and shift operation in the 4 layer 3D vertical TiN/Ti/HfO $_{x}$ /TiN RRAM array [108].

    IBM utilizing RRAM's character of in-situ data process and storage, with the simple AND logic, greatly enhanced the training and learning ability of neuron networks by 620 to 31 000 times [129]. They proposed a concept of a resistive processing unit (RPU) which is designed to improve deep neural networks (DNN) training efficiency while consuming much less power. By storing and updating the weight values locally, data movement during training is minimized and the parallelism of the training algorithm is fully exploited, as is shown in Fig. 14.

    Huang et al. of the Peking University reported a new computer unit built based on the resistance switching crossbar array, where logic and memory functions are performed in the same devices, as shown in Fig. 15 [130]. In the new computer unit, nonvolatile NAND and AND logic operations are performed by resistive switching devices through the interaction between resistance states. By combining NAND and AND logic operations, resistance states stored in RS devices located in arbitrary positions can perform various logic operations by logic cascading, such as full adder. The logic functions can be reconfigured by altering trigger signals. The nonvolatile logic operations in the resistive switching crossbar array with resistance as a physical variable offer a new technology solution to conventional computation system problems.

    The non-volatility of the RRAM devices can support the realization of low power and nonvolatile logic circuits. One of the challenges that nonvolatile logic faces is the requirements of fast switching speed, high endurance and high reliability for the RRAM devices. Many efforts are needed to deeply understand the basic principles of logic operations and related control methods.

5.   Conclusion
  • RRAM has progressed rapidly in the past several years with advances that range from excellent device performance to 3D integration demonstration, showing great potential in high-density memory and nonvolatile logic applications. However, several challenges remain before RRAM is ready for practical applications. More complete understanding of the microscopic conduction and switching process are necessary to reveal the nature of resistive switching. RRAM device characteristics should be optimized and controlled carefully to meet different application needs. Selecting a device with excellent performance is key for RRAM array operation. The selectors need a great technological breakthrough to support the reliable operation in large-scale crossbar RRAM array. With rapid progress, it is believed that RRAM will play an important role in future technology like high-density storage and nonvolatile logic application.

Figure (15)  Table (2) Reference (134) Relative (20)

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