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Volume 38, Issue 7, Jul 2017

# INVITED PAPERS

• ## Studies of Water V. Five Phonons in Protonic Semiconductor Lattice Model of Pure Liquid Water

J. Semicond.  2017, 38(7): 071001

doi: 10.1088/1674-4926/38/7/071001

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We report physics based confirmation (1% RMS deviation), by existing experimental data, of proton-prohol (proton-hole) ion product (pH) and mobilities in pure liquid water (0-100℃, 1-atm pressure) anticipated from our melted-ice Hexagonal-Close-Packed (H2O)4 Lattice Model. Five phonons are identified. (1) A propagating protonic phonon (520.9 meV from lone-pair-blue-shifted stretching mode of isolated water molecule) absorbed to generate a proton-prohol pair or detrap a tightly-bound proton. (2) Two (173.4 and 196.6 meV) bending-breathing protonic-proholic or protonic phonons absorbed during de-trapping-limited proton or proton-prohol mobilities. (3) Two propagating oxygenic-wateric Debye-Dispersive phonons (30.3 and 27.5 meV) absorbed during scattering-limited proton or proton-prohol mobilities.

• # INVITED REVIEW PAPERS

• ## Resistive random access memory and its applications in storage and nonvolatile logic

J. Semicond.  2017, 38(7): 071002

doi: 10.1088/1674-4926/38/7/071002

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The resistive random access memory (RRAM) device has been widely studied due to its excellent memory characteristics and great application potential in different fields. In this paper, resistive switching materials, switching mechanism, and memory characteristics of RRAM are discussed. Recent research progress of RRAM in high-density storage and nonvolatile logic application are addressed. Technological trends are also discussed.

• # SEMICONDUCTOR PHYSICS

• ## Substrate temperature effect on the photophysical and microstructural properties of fluorine-doped tin oxide nanoparticles

J. Semicond.  2017, 38(7): 072001

doi: 10.1088/1674-4926/38/7/072001

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Transparent conducting oxide of fluorine-doped tin oxide (FTO) thin films was deposited from chemical solutions of tin chloride and ammonium fluoride using streaming process for electroless and electrochemical deposition (SPEED) at substrate temperature 450, 500, and 530 ℃ respectively. The effect of substrate temperatures on the microstructural properties such as crystallite size, dislocation density, micro strain, volume of the unit cell, volume of the nanoparticles, number of the unit cell, bond length and the lattice constants were examined using XRD technique. Only reflections from (110) and (200) planes of tetragonal SnO2 crystal structure were obvious. The peaks are relatively weak indicating that the deposited materials constitute grains in the nano dimension. Hall measurements, which were done using van der Pauw technique, showed that the FTO films are n-type semiconductors. The most favorable electrical values were achieved for the film grown at 530 ℃ with low resistivity of 7.64×10-4Ω·cm and Hall mobility of -9.92 cm2/(V·s).

• # SEMICONDUCTOR MATERIALS

• ## The electronic and magnetic properties of wurtzite Mn:CdS, Cr:CdS and Mn:Cr:CdS: first principles calculations

J. Semicond.  2017, 38(7): 073001

doi: 10.1088/1674-4926/38/7/073001

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In this article, density functional theory (DFT) based on generalized gradient approximation (GGA) and GGA+U, U is Hubbard term, is used to study the electronic properties of CdS doped with different dopants (Cr, Mn). The calculations are carried out for Mn-doped CdS, Cr-doped CdS, and co-doping of Mn/Cr in CdS simultaneously. It is found that hopping of electrons is possible with Cr:CdS and Mn:Cr:CdS while Mn:CdS does not allow the hopping of electrons. Moreover, double exchange interactions are observed in Cr:CdS and d-d super-exchange interactions are observed in Mn:CdS. Now the problem becomes interesting when one magnetic ion (Cr) supporting double exchange interactions and another ion (Mn) supporting d-d super-exchange interactions are doped simultaneously in the same system (CdS). The co-doped CdS is more stable even at high Curie temperature due to p-d double exchange interactions and d-d super exchange interactions. Furthermore, the Cr-3d and Mn-3d states present in-between the band gap are responsible for inner shell transitions and hence for optical properties. Therefore, the co-doped system is taken into account to enhance its applications in the field of spintronic and magneto-optical devices.

• ## Photoelectrochemical performance of La3+-doped TiO2

J. Semicond.  2017, 38(7): 073002

doi: 10.1088/1674-4926/38/7/073002

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La-doped TiO2 thin films on titanium substrates were prepared by the sol-gel method with titanium tetrachloride as a precursor and La2O3 as a source of lanthanum. The heat-treatment temperature dependence of the photoelectrochemical performance of the La-doped TiO2 film in 0.2 mol/L Na2SO4 was investigated by the Mott-Schottky equation, electrochemical impedance spectroscopy, and the open-circuit potential test. The results from the Mott-Schottky curves show that the obtained films all were n-type semiconductors, and the film at 300 ℃ had the highest conduction band position and the widest space charge layer. The electrochemical impendence spectroscopy (EIS) tests of the 300 ℃ film decreased most during the change from illuminated to dark. The potential of the La-TiO2 thin film electrode was the lowest after the 300 ℃ heat treatment. The open-circuit potential indicated that the photoelectrical performance of the La-TiO2 films was enhanced with the addition of the La element and the largest decline (837.8 mV) in the electrode potential was achieved with the 300 ℃ heat treatment.

• # SEMICONDUCTOR DEVICES

• ## Design and simulation of a novel E-mode GaN MIS-HEMT based on a cascode connection for suppression of electric field under gate and improvement of reliability

J. Semicond.  2017, 38(7): 074001

doi: 10.1088/1674-4926/38/7/074001

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We proposed a novel AlGaN/GaN enhancement-mode (E-mode) high electron mobility transistor (HEMT) with a dual-gate structure and carried out the detailed numerical simulation of device operation using Silvaco Atlas. The dual-gate device is based on a cascode connection of an E-mode and a D-mode gate. The simulation results show that electric field under the gate is decreased by more than 70% compared to that of the conventional E-mode MIS-HEMTs (from 2.83 MV/cm decreased to 0.83 MV/cm). Thus, with the discussion of ionized trap density, the proposed dual-gate structure can highly improve electric field-related reliability, such as, threshold voltage stability. In addition, compared with HEMT with field plate structure, the proposed structure exhibits a simplified fabrication process and a more effective suppression of high electric field.

• ## A 0.02% THD and 80 dB PSRR filterless class D amplifier with direct lithium battery hookup in mobile application

J. Semicond.  2017, 38(7): 074002

doi: 10.1088/1674-4926/38/7/074002

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This paper presents a fully integrated CMOS filterless class D amplifier that can directly hook up lithium battery in mobile application The proposed amplifier embodies a 2-order feedback path architecture instead of direct feedback of output to input of the integrator to decrease the high frequency intermodulation distortion associated with direct feedback and eliminate the integrator input common mode disturbance from the output in ternary modulation. The prototype class D amplifier realized in 0.35μm digital technology achieves a THD+N of 0.02% when delivering 400 mW to an 8Ω load from VDD=3.6 V. The PSRR of the prototype class D amplifier is 80 dB at 217 Hz. Furthermore a filterless method that can eliminate the external LC filter is employed which offers great advantages of saving PCB space and lowering system cost. In addition the prototype class D amplifier can operate in large voltage range with VDD range from 2.5 to 4.2 V in mobile application. The total area of the amplifier is 1.7 mm2.

• ## Analysis of DC and analog/RF performance on Cyl-GAA-TFET using distinct device geometry

J. Semicond.  2017, 38(7): 074003

doi: 10.1088/1674-4926/38/7/074003

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In this paper, analysis of DC and analog/RF performance on cylindrical gate-all-around tunnel field-effect transistor (TFET) has been made using distinct device geometry. Firstly, performance parameters of GAA-TFET are analyzed in terms of drain current, gate capacitances, transconductance, source-drain conductance at different radii and channel length. Furthermore, we also produce the geometrical analysis towards the optimized investigation of radio frequency parameters like cut-off frequency, maximum oscillation frequency and gain bandwidth product using a 3D technology computer-aided design ATLAS. Due to band-to-band tunneling based current mechanism unlike MOSFET, gate-bias dependence values as primary parameters of TFET differ. We also analyze that the maximum current occurs when radii of Si is around 8 nm due to high gate controllability over channel with reduced fringing effects and also there is no change in the current of TFET on varying its length from 100 to 40 nm. However current starts to increase when channel length is further reduced for 40 to 30 nm. Both of these trades-offs affect the RF performance of the device.

• ## 152 W high-power blue diode laser operated at 447 nm

J. Semicond.  2017, 38(7): 074004

doi: 10.1088/1674-4926/38/7/074004

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We demonstrate a high-power blue diode laser operated at 447 nm combining laser diodes using an optical fiber bundle. As many as 127 diode lasers at 447 nm were coupled into 400 μm/0.22NA fibers using an aspherical lens group with different focus lengths. The bare fibers were mechanically bundled through high temperature ultraviolet adhesive after the coatings of the 127 fibers were stripped. The diameter of the fiber bundle was 6 mm. The total output power of such a bundle was 152 W with electro-optical conversion efficiency of 27.56% and the RMS power instability was less than ± 1% within 3 h.

• ## Broad area quantum cascade lasers operating in pulsed mode above 100 ℃ at λ~4.7μm

J. Semicond.  2017, 38(7): 074005

doi: 10.1088/1674-4926/38/7/074005

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We demonstrate a broad area (400 μm) high power quantum cascade laser (QCL). A total peak power of 62 W operating at room temperature is achieved at λ~4.7 μm. The temperature dependence of the peak power characteristic is given in the experiment, and also the temperature of the active zone is simulated by a finite-element-method (FEM). We find that the interface roughness of the active core has a great effect on the temperature of the active zone and can be enormously improved using the solid source molecular beam epitaxy (MBE) growth system.

• ## Study on the mechanism of color coordinate shift of LED package

J. Semicond.  2017, 38(7): 074006

doi: 10.1088/1674-4926/38/7/074006

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In the paper, the influences of the chip, silicone and phosphors on the color coordinate shift of LED were studied. In the process of LED baking, it was found that the effect of the chip and silicone on the color coordinate drift is less than 3% through the analysis of each influencing factor. But the influence of the phosphors is large and accounted for 11.11% of the overall impact factors. Therefore, it is important to select the better green phosphors in thermal stability for the LED package and it has a guiding significance to the color coordinate of LED distribution.

• ## Application of resist-profile-aware source optimization in 28 nm full chip optical proximity correction

J. Semicond.  2017, 38(7): 074007

doi: 10.1088/1674-4926/38/7/074007

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As technology node shrinks, aggressive design rules for contact and other back end of line (BEOL) layers continue to drive the need for more effective full chip patterning optimization. Resist top loss is one of the major challenges for 28 nm and below technology nodes, which can lead to post-etch hotspots that are difficult to predict and eventually degrade the process window significantly. To tackle this problem, we used an advanced programmable illuminator (FlexRay) and Tachyon SMO (Source Mask Optimization) platform to make resist-aware source optimization possible, and it is proved to greatly improve the imaging contrast, enhance focus and exposure latitude, and minimize resist top loss thus improving the yield.

• ## Temperature characteristics research of SOI pressure sensor based on asymmetric base region transistor

J. Semicond.  2017, 38(7): 074008

doi: 10.1088/1674-4926/38/7/074008

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Based on the asymmetric base region transistor, a pressure sensor with temperature compensation circuit is proposed in this paper. The pressure sensitive structure of the proposed sensor is constructed by a C-type silicon cup and a Wheatstone bridge with four piezoresistors (R1, R2, R3 and R4) locating on the edge of a square silicon membrane. The chip was designed and fabricated on a silicon on insulator (SOI) wafer by micro electromechanical system (MEMS) technology and bipolar transistor process. When the supply voltage is 5.0 V, the corresponding temperature coefficient of the sensitivity (TCS) for the sensor before and after temperature compensation are -1862 and -1067 ppm/℃, respectively. Through varying the ratio of the base region resistances r1 and r2, the TCS for the sensor with the compensation circuit is -127 ppm/℃. It is possible to use this compensation circuit to improve the temperature characteristics of the pressure sensor.

• # SEMICONDUCTOR INTEGRATED CIRCUITS

• ## Insight into multiple-triggering effect in DTSCRs for ESD protection

J. Semicond.  2017, 38(7): 075001

doi: 10.1088/1674-4926/38/7/075001

Abstract Full Text PDF Get Citation

The diode-triggered silicon-controlled rectifier (DTSCR) is widely used for electrostatic discharge (ESD) protection in advanced CMOS process owing to its advantages, such as design simplification, adjustable trigger/holding voltage, low parasitic capacitance. However, the multiple-triggering effect in the typical DTSCR device may cause undesirable larger overall trigger voltage, which results in a reduced ESD safe margin. In previous research, the major cause is attributed to the higher current level required in the intrinsic SCR. The related discussions indicate that it seems to result from the current division rule between the intrinsic and parasitic SCR formed in the triggering process. In this letter, inserting a large space into the trigger diodes is proposed to get a deeper insight into this issue. The triggering current is observed to be regularly reduced along with the increased space, which confirms that the current division is determined by the parasitic resistance distributed between the intrinsic and parasitic SCR paths. The theoretical analysis is well confirmed by device simulation and transmission line pulse (TLP) test results. The reduced overall trigger voltage is achieved in the modified DTSCR structures due to the comprehensive result of the parasitic resistance vs triggering current, which indicates a minimized multiple-triggering effect.

• ## A small signal coupling model for predicting the coupling between LNAs

J. Semicond.  2017, 38(7): 075002

doi: 10.1088/1674-4926/38/7/075002

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A small signal coupling model is developed to analyze the coupling between two LNAs. The mutual inductance between the adjacent on-chip inductors is considered responsible for this coupling. A set of formulas have been derived to quantitatively predict the coupling effects. Based on our analysis, a quick estimation can be made to see which pair of inductors plays a key role in evaluating the coupling between the LNAs. Source inductors of two LNAs are placed closely while the load inductors are far apart according to the analysis. To validate the proposed theory, two 2 GHz LNAs are fabricated. The LNAs have a peak gain of 18 dB and NF of 1.4 dB. The coupling between the LNAs is -30 dB.

J. Semicond.  2017, 38(7): 075003

doi: 10.1088/1674-4926/38/7/075003

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A new loading-balanced architecture for high speed and low power consumption pipeline analog-to-digital converter (ADC) is presented in this paper. The proposed ADC uses SHA-less, op-amp and capacitor-sharing technique, capacitor-scaling scheme to reduce the die area and power consumption. A new capacitor-sharing scheme was proposed to cancel the extra reset phase of the feedback capacitors. The non-standard inter-stage gain increases the feedback factor of the first stage and makes it equal to the second stage, by which, the load capacitor of op-amp shared by the first and second stages is balanced. As for the fourth stage, the capacitor and op-amp no longer scale down. From the system's point of view, all load capacitors of the shared OTAs are balanced by employing a loading-balanced architecture. The die area and power consumption are optimized maximally. The ADC is implemented in a 0.18 μm 1P6M CMOS technology, and occupies a die area of 1.2×1.2 mm2. The measurement results show a 55.58 dB signal-to-noise-and-distortion ratio (SNDR) and 62.97 dB spurious-free dynamic range (SFDR) with a 25 MHz input operating at a 200 MS/s sampling rate. The proposed ADC consumes 115 mW at 200 MS/s from a 1.8 V supply.

• ## A high-accuracy DCO with hybrid architecture

J. Semicond.  2017, 38(7): 075004

doi: 10.1088/1674-4926/38/7/075004

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In this paper, a novel hybrid digital-controlled oscillator (DCO) is proposed, which is used to improve the accuracy of the all-digital clock generator without reference source. The DCO with hybrid architecture consists of two parts: DCO_high and DCO_low. The DCO_high decides the coarse output frequency of DCO, and adopts the cascade structure to decrease the area. The DCO_low adopts the chain structure with three-state buffer, and decides the fine output frequency of DCO. Compared with traditional cascade DCO, the proposed hybrid DCO features higher precision with less inherent delay. Therefore the clock generator can tolerate process, voltage and temperature (PVT) variation and meet the needs of different conditions. The DCO is designed in SMIC 180 nm CMOS process with 0.021 mm2 chip area. The output frequency is adjusted from 15-120 MHz. The frequency error is less than 0.83% at 25 MHz with 1.6-1.8 V supply voltage and 0-80 ℃ temperature variations in TT, FF, SS corners.

• ## A low noise interface circuit design of micro-machined gyroscope

J. Semicond.  2017, 38(7): 075005

doi: 10.1088/1674-4926/38/7/075005

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The analyses of MEMS gyroscope interface circuit on thermal noise, 1/f noise and phase noise are made in this paper. A closed-loop differential driving circuit and a low-noise differential detecting circuit based on the high frequency modulation are designed to limit the noise. The interface chip is implemented in a standard 0.5 μ m CMOS process. The test results show that the resolution of sensitive capacity can reach to 6.47 × 10-20 F at the bandwidth of 60 Hz. The measuring range is ± 200°/s and the nonlinearity is 310 ppm. The output noise density is 5.8°/(h·\begin{document}$\sqrt {\rm{Hz}}$\end{document}). The angular random walk (allen-variance) is 0.092°/\begin{document}$\sqrt {\rm{h}}$\end{document} and the bias instability is 2.63°/h.