A 4 Gbps current-mode transmitter for 12-bit 250 MSPS ADC

    Corresponding author: Zongguang Yu, yuzg@sina.com
  • 1. China Electronic Technology Group Corporation, No. 58 Research Institute, Wuxi 214035, China
  • 2. Wide Bandgap Semiconductor Technology Disciplines State Key Laboratory, Xidian University, Xi'an 710071, China
  • 3. School of Information Engineering, Huangshan University, Huangshan 245041, China

Key words: interfacepipelined ADCtransmittercurrent mode

Abstract: A 4 Gbps transmitter for a 12-bit 250 MSPS pipelined ADCs is presented. A low power current mode (CM) output driver with reverse scaling technique is proposed. A high speed, low power combined serializer is implemented to convert 12 bit parallel data into a seria1 data stream. The whole transmitter is used in a 12-bit 250 MSPS pipelined ADC for the digital output buffer and fabricated in 180 nm 1. 8 V 1P5M CMOS technology. Test results show that the transmitter provides an eye height greater than 800 mV for data rates of both 2 Gbps and 4 Gbps, the 12-bit 250 MSPS ADC achieves the SNR of 69.92 dBFS and SFDR of 81.17 dB with 20.1 MHz input at full sampling speed. The ADC with the 4 Gbps transmitter consumes the power consumption of 395 mW, where the power consumption of transmitter is 75 mW. The ADC occupies an area of 2.5×3.2 mm2, where the active area of the transmitter block is 0.5×1.2 mm2.

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1.   Introduction
  • With the rapid increase of the required data processing rate for digital processors such as SoCs, DSPs and FPGAs, chip-to-chip communications has developed continually to provide high transmission speed with good signal integrity (SI) and low power consumption [1, 2]. The sampling rate of high speed ADCs has increased from MHz to GHz, which requires the digital output interface to transmit the digital output code with the data rate over 1 Gbps. In order to speed up the data rates of the digital outputs interface for high speed ADCs, LVDS transmitters are widely used to provide output rates from 100 MHz to 1 GHz. However, when multi-channel ADCs are integrated on the single chip, the output pin numbers for LVDS output transmitters become a bottle-neck for packaging and PCB layout. Meanwhile, the current consumption for those LVDS transmitters occupies a considerable part of the overall power consumption.

    In this paper, a current mode (CM) based transmitter is presented to offer a solution to transmit high speed digital outputs with large trace length and very low bit error rate for a 12-bit 250 MSPS pipelined ADC in a 1P5M 0. 18 $\mu$m CMOS process. To fulfill the design target, the data from the 12-bit ADC is sent serially in packets of 64 bits, which consist of an 8-bit header, 48-bit data, and 8-bit error correction code (ECC). The output data streaming of 16 × the encode clock is designed for the transmitter to drive the digital output code of the 12-bit 250 MSPS ADC at the data transmission rate of 4 Gbps.

2.   System architecture
  • The transmitter is designed to drive the high speed signal from on the chip to the devices on of-chip transmission lines. The structure of the 4 Gbps CM based transmitter for 12-bit 250 MSPS pipelined ADC is shown in Fig. 1. The transmitter is composed of an encoder which converts the parallel 12-bit code to a 64-bit code, a serializer which changes the parallel 64-bit code to the serial packets of 64 bits under the clock of 2 GHz, and a CM driver that drives the serialized data stream Din to differential output of Dout+ and Dout-.

    The output data streaming of 16 × the encode clock is designed for the transmitter to drive the digital output code of the 12-bit 250 MSPS ADC at the data transmission rate of 4 Gbps. The timing diagram and packet protocol of the transmitter are shown in Fig. 2. The data from the 12-bit 250 MSPS ADC is sent serially in packets of 64 bits, which consist of an 8-bit header, 48-bit data, and 8-bit ECC. The 48-bit data is composed of 4 rows of consecutive 12-bit parallel digital conversion code D1, D2, D3 and D4 from the digital correction logic of the pipelined ADC. The parallel code D1 to D4 are firstly aligned and processed by the scramble & ECC block to get the parallel 64-bit data packet. The data packets from the encoder are then serialized by the serializer with a 2 GHz clock and get the serialized data stream Din. Finally, Din is transmitted by the CM driver to the differential output of Dout+ and Dout-at the data transmission rate of 4 Gbps.

  • 2.1.   Scramble

  • There are two scramblers used on the transmitter, which are an Ethernet scrambler ($x^{\mathrm{58}} + x^{\mathrm{39}} + 1$) and a SONET scrambler ($x^{\mathrm{7}} + x^{\mathrm{6}} + 1$). The scramblers are used to help balance the number of 1 s and 0 s in the packet. Fig. 3 shows the serial implementation of the Ethernet and SONET scramblers. Both Ethernet and SONET scramblers work on scrambling the whole packet (64 bits), the header and the data (56 bits), or just the data (48 bits). The parallel implementation allows the scrambler and descrambler to run at a slower clock rate. For the scrambler, 64 bits are processed even in the 56-and 48-bit cases. To achieve this for 56 bits, a portion of ECC data is used to fill the rest of the input word; for 48 bits, a portion of header and ECC data are used to fill the rest of the input word.

  • 2.2.   ECC

  • The 8 bits code ECC is implemented by the Hamming code. The 64-Bit Packet for calculating the ECC code is shown in Fig. 4. The MSB parity bits hold on 0. The p7 parity bits for the entire packet are the XOR result of p1-p6, calculated after the other parity bits are calculated. The p6 to p1 parity bits for the entire packet are calculated in Table 1, each parity bit is the XOR result of parity calculating bits.

3.   Circuit implementation

    3.1.   Serializer

  • The serializer is used to convert the 64 bit parallel data into 4 Gbps serial stream for the CM driver. Fig. 5 shows the architecture of the serializer. It multiplies the synchronized 250 MHz parallel data to 4 Gbps serial stream. The 64 bits parallel data is firstly divided into 8-bit data by 8 : 1 MUX, and each of the 8-bit data is delivered to an 8-bit CML shifter. The shifter is driven by a couple of 2 GHz clocks. The 8-bit CML shifter consists of 2 channels of 4 CML latch chains. In this module 8-bit parallel data is transformed into a 4Gbps serial data stream.

  • 3.2.   CM output driver

  • The differential output driver is one of the most important parts of the transmitter, as it is the bottleneck of the bandwidth and usually consumes most of the power of the whole transmitter. The output driver usually employs differential data transmission to improve the immunity and compliance to the noise. It is a switch bridge driving a differential 100 $\Omega $ load resistor[3]. There are generally two different architectures used for output drivers: voltage mode (VM) and current mode (CM). The VM output driver consumes about 1/4 the output driver power of the CM, but it has difficulties in achieving constant current and area efficiency. The CM output driver has high output impedance that has less impact on the termination impedance. So it offers better SI performance than that of VM output drivers[8]. The CM output driver is selected for the transmitter to achieve higher output signal swing, as is shown in Fig. 6.

    The CM driver circuit consists of a single ended to differentia1 circuit and a differential CM driving stage circuit. The single ended to differential circuit is mainly digital circuitry, which is implemented by cascaded inverter buffer stages. The driving stage consists of a full switch bridge pre-driving stage and a primary driving stage circuit. Vbiasp and Vbiasn are the bias signals to ensure the 4 mA output driving current.

  • 3.3.   PLL

  • A fully integrated PLL is designed to provide the clock network for the whole system without any externa1 component. The general architecture of the proposed PLL frequency synthesizer is shown in Fig. 7. It consists of the PREDIVIDER, phase/frequency detectors (PFD), charge pump (CP) and low pass loop filter (LPF), PreVC, voltage controlled oscillator (VCO), DIVIDER and Buffer. The PREDIVIDER first divides the external clock signal as a reference clock ($f_{\mathrm{ref}})$. The PFD detects the phase and frequency difference between the reference clock ($f_{\mathrm{ref}})$ and the feedback clock ($f_{\mathrm{back}})$, and generates the UP and DN switching pulses. The output current from the CP is switched on or off by these UP and DN pulses to charge or discharge the capacitor in the LPF, and the output voltage of the LPF is the control signal VC. In order to get the differential control voltage for VCO, a PreVC circuit is used. The output signal frequency of the VCO is sent back to the PFD after being divided by the DIVIDER. The Buffer is used so that the VCO is separated from the output. Also, the Buffer converts the output voltage from VCO to a current signal; therefore, the transmission loss is significantly reduced.

    The PreVC generates the bias voltages VCP and VCN from VC. It ensures that the VCO voltage is continuously adjusted so that the lower swing limitation of VC for the VCO is correctly provided. So a constant voltage which is independent of supply voltage is established. In order to solve the problem, a differential amplifier and a half-buffer replica are used. The voltage at the output of the half-buffer replica is set equal to VC via VCN adjustments generated by the amplifier. If the supply voltage changes, the amplifier will adjust accordingly to keep the bias current as a constant.

4.   Structure of the 12-bit 250 MSPS ADC
  • The block diagram of the 12-bit 250 MSPS pipelined ADC is shown in Fig. 8 which is composed of a high-speed low-distortion sample and hold circuit, a 4.5-bit first stage, 3 consecutive 2.5-bit sub-stages and a final 3-bit flash. All together there are 13-bit codes generated, only the header 12-bit is chosen for the ADC. The ADC is implemented in switched capacitor scheme. The ADC includes an on-chip precision bandgap reference voltage generator and buffer amplifiers. As a non-overlapping 4-phase clock with over 200 MHz frequency is used, the clock generation of the ADC is implemented with distributed clock generators. The 12 bits digital output codes from the digital correction block are transported to the 4 Gbps transmitter getting the CML output code.

5.   Chip measurements
  • The 4 Gbps transmitter for a 250-MSPS, 12-bit ADC has been fabricated in a 0.18-$\mu $m 1.8 V 1P5M mix-signal CMOS process. The die photograph is shown in Fig. 9(a). The central part is the SHA circuit and the 5 connective pipeline sub-stages, and the upper side shows reference voltage generator and buffer opamps, the digital error correction logic block follows the pipelined stages, the PLL and clock buffer is in the lower left of the chip and the scramble & ECC block is in the lower right of the prototype ADC. The total die area is about 2.5 × 3.2 mm$^{\mathrm{2}}$, where the active area of the 12-bit pipelined ADC core is 2.1 × 1.2 mm$^{\mathrm{2}}$, the die area of the PLL is 0.5 × 1.2 mm$^{\mathrm{2}}$ the active area of the scramble & ECC block is 0.5 × 1.1 mm$^{\mathrm{2}}$, and the active area of the driver is 4 × 5 mm$^{\mathrm{2}}$.

    The measured 32 K point output fast Fourier transform (FFT) spectrum with 20.1 MHz input frequency at 250-MSPS is shown in Fig. 9(b). The measured signal-to-noise-ratio (SNR) is 69.92 dB FS the spurious free dynamic range (SFDR) is 81.17 dB and the effective number of bits (ENOB) is 11.3. The measured nonlinearity of the ADC is shown in Figs. 9(c)-9(d). The integral nonlinearity (INL) is -0.4/+0.6 LSB and the differential nonlinearity (DNL) is -0.22/+0.16 LSB. As no other calibration is used in the prototype ADC, the INL graph shows big transitions for codes at the 16 thresholds of the 4.5-bit first stage of the pipelined ADC. The total ADC power consumption on a 1.8 V supply is about 395 mW, where the power consumption of the 4 Gbps transmitter is about 75 mW, and the power consumption of the PLL in the transmitter is 35 mW.

    The measured eye-diagram and the transient waveform are shown in Fig. 10. The driver current is derived on chip and sets the output current at each output equal to a nominal 4 mA. A 100 $\Omega $ differential termination resistor is placed at the FPGA receiver input to result in a nominal differential 800 mVp-p swing. The transient differential waveform of the digital output data under 250 MSPS is given in Figs. 10(a) and 10(b); we can see that the signal swing of the transmitter is 800 mV p-p. Fig. 10(a) shows the transient signal of the digital output when the scramble function is off; the 64-bit data package occupies the time of 16 ns, which is 4 clock periods of the sampling clock. When the scramble function is off, the 8-bit header and 8-bit ECC code in the 64-bit data package are 0. Fig. 10(b) shows the transient signal of the digital output when the scramble function is on, the 8-bit header and 8-bit ECC code are no longer 0 s, and the number of 1 s and 0 s in the corresponding 64-bit data packet are properly balanced. The eye-diagram and a time interval error (TIE) jitter histogram of the transmitter are shown in Figs. 10(c) and (d). Fig. 10(c) shows the measured results when the transmitter works at 4 Gbps, it can be seen from the figure that the differential eye opening is 80 mV, and the peak-to-peak jitter is about 80 ps. The root mean square (RMS) jitter is about 160 ps corresponding to about 36% of the output period Fig. 10(d) shows the measured results when the transmitter works at 2 Gbps; it can be seen from the figure that the peak-to-peak jitter is about 120 ps. The RMS jitter is about 230 ps, corresponding to about 24% of the output period.

    The performance of the proposed transceiver is summarized and compared with recent works with similar architecture in Table 2. Table 3 shows the performance comparison of the 12-bit 250 MSPS pipelined ADC with other recent 12-bit high speed ADC works.

6.   Conclusion
  • A 4 Gbps transmitter for a 12-bit high speed ADC is presented. A low power CM output driver with reverse scaling technique is proposed. A high speed, low power combined serializer is implemented to convert 12 bit parallel data into a seria1 data stream. The whole transmitter is used in a 12-bit 250 MSPS pipelined ADC for the digital output buffer and fabricated in 180 nm 1.8 V 1P5M CMOS technology. Test results show that the transmitter provides an eye height greater than 800 mV for data rates of both 2 Gbps and 4 Gbps and consumes 75 mW at 4 Gbps, the 12-bit 250 MSPS ADC achieves the SNR of 69.92 dBFS and SFDR of. 81.17 dB with 20.1 MHz input at full sampling speed. The ADC with the 4 Gbps transmitter consumes the power consumption of 395 mW and occupies an area of 2.5 × 3.2 mm$^{\mathrm{2}}$, where the active area of the transmitter block is 0.5 × 1.5 mm$^{\mathrm{2}}$.

Figure (10)  Table (3) Reference (13) Relative (20)

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