Nowadays, the complementary metal-oxide semiconductor (CMOS) chips’ feature size has commercially developed to 5 nm. FinFETs are promising to extend CMOS scaling owing to reduced short-channel effects. Compared with planar devices, FinFET has the following advantages, such as near-ideal subthreshold slope, excellent gate control over the body potential, low leakage current and higher mobility. On behalf of the high-performance device, FinFET also attracts the attention of applications in radiation environment, such as in space.
However, there are some serious reliability problems for aerospace devices, such as HCI and radiation damages. Channel hot carriers are generated by impact ionization under the action of a strong electric field near the drain. When these carriers are launched to the gate, oxide layer trap charges and interface states will be generated, which will affect the performance parameters of the devices, such as threshold voltage, subthreshold swing, saturation current and trans-conductance, etc. The FinFET with a small feature size has a strong internal electric field, thus the HCI can be significant. Some studies show that HCI is dependent on fin width. Ma pointed out that parameter degradation caused by 14 nm FinFET HCI is mainly attributed to interface states, and the distribution of interface states on the top of FinFET fins is significantly less than that on the lateral wall of fins. After studying the HCI of 90 nm SOI FinFET with different channel lengths, Jiang pointed out that the degradation mechanism of long-channel devices and short-channel devices is different. Yeh pointed out that 20 nm bulk FinFET with fewer fins show better device characteristics, but the degradation of device parameters caused by hot carriers is more serious. Moreover, different evolutions of the threshold voltage and the saturation current of the UTBB nMOSFETs may be due to the slow border traps.
For devices used in a radiation environment, not only the conventional reliability problems should be considered, but also the influence of radiation effects on the conventional reliability of devices should be paid attention to. Silvestri pointed out that, for 130 nm NMOSFETs, the parameter degradation of the un-irradiated nMOSFETs is smaller than that of the irradiated sample after applying hot carrier stress. The larger the bias, the smaller the degradation of device parameters. Zheng pointed out that hot carrier degradation of irradiated 65 nm nMOSFETs is greater than those without irradiation due to radiation-induced charge trapping in the STI. The influence of TID (total ionizing dose effect) on HCI of short channel UTBB FD-SOI nMOSFETs is significant, which is due to irradiation generated defects in buried oxide (BOX). For nMOSFET, the synergistic effect of total dose irradiation and hot carriers exceeds the simple superposition of the two effects. It considers that the combination of holes in the oxide trap induced by the total dose irradiation and hot electrons reduces the positive charge in the oxide trap. The irradiation-induced interface state captures the hot electrons to form negative interface trap charges. But, to the best of our knowledge, no studies have shown how total ionizing dose radiation affects HCI in 22 nm FinFETs.
The HCI of nFinFET with different fin numbers and the influence of total ionizing dose irradiation with different bias conditions on the HCI of nFinFET are studied in the paper. We demonstrate that the smaller the fin number, the more obvious the HCI of nFinFETs. What is more, compared with un-irradiated nFinFET, the HCI of irradiated nFinFET is weakened, which is different from the experimental phenomena of planar devices.