Fig. 1 shows the Raman spectra and XRD pattern of the three diamond samples. It can be seen that the background of the sample I-PC is very small. But for the samples II-PC and III-SC, the background line shows a significant upward movement, which is proven to be due to the increase of defect and impurity content. This indicates that the quality of sample II-PC is poor. Sample III-SC also has some defects and impurities. And sample I-PC shows high quality. We measured the nitrogen content of the three samples by secondary ion mass spectroscopy (SIMS) and found that the nitrogen content for II-PC sample is 0.23 ppm, and III-SC sample is 0.21 ppm. And for the I-PC sample, the nitrogen content is under the detection limit of SIMS. Nitrogen should be the main impurities in the samples.
The gate length and source–drain space of the three diamond samples were shown in Table 1[5, 10, 11]. As shown in Table 1, the polycrystalline diamond FETs (I-PC and II-PC) show higher maximum saturation source–drain current Ids than the single crystal diamond FET (III-SC). This may be due to the different orientations of the single crystal and polycrystalline diamond samples. The orientation of the single crystal diamond is (001). The polycrystalline diamond samples are composed of grains with different orientations, including (111), (220), and (311), as shown in Fig. 1(b). As reported by Sato et al., the sheet density of (110), and (111) H-terminated surfaces are higher than that of (100) surfaces. From first-principle calculations, the VBM level is the highest for (110), second highest for (111), and the lowest for (100) and the hole concentration depends on the C–H bond density. And the values of their maximum transconductance gm are comparable for the three samples.
Pulsed I–V characteristics for the III-SC sample at different quiescent bias points were measured, as shown in Fig. 2. The measured results for the I-PC and II-PC samples have been shown in our previous work[5, 11]. The setting conditions for pulsed I–V characteristics measurements are the same with our previous work. It was found that for all the three samples, the gate-lag effect (traps respond to the gate voltage) is negligible. The drain-lag effect (traps responded to the drain voltage) induces the maximum drain current decrease, as shown in Fig. 2(b). The maximum drain current degeneration values induced by drain-lag effect are 2.7%, 10%, and 3.7%, respectively, as shown in Table 1. Combined with the Raman results in Fig. 1(a), the high defect concentration and impurity content in the diamond samples, the large drain-lag effect exists in the FETs. This indicates that the N impurities and defects in the diamond will act as traps in the carrier transport.
The small signal S-parameters of the diamond FETs were measured between 0.1–30 GHz[5, 10, 11]. Open and short structures were used to remove the parasitic elements. The relationship of current cut-off frequency fT and gate length (Lg) of the diamond FETs is shown in Fig. 3[2-4, 15-18]. The extrinsic saturation drift velocities vs of the three samples (I-PC, II-PC, and III-PC) are all around 5 × 106 cm/s, as shown in Fig. 3.
The component parameters of the three diamond samples extracted from the small single parameters are shown in Table 2. The three samples show comparable cut-off frequency fT, but fmax values show big difference. The extrinsic fmax for transistors can be expressed as
It can be seen that the parasitic resistance has strong influence on the extrinsic fmax for transistors. The fmax value of sample II-PC is the lowest. This is due to its rectangular gate structure, which makes the gate resistance Rg large, as shown in Table 2.
Fig. 4 shows the RF power output characteristic measured at 2 GHz under a continuous-wave signal (A-class) for the I-PC diamond FET. As shown in the figure, the maximum gain is 18.3 dB and the power added efficiency (PAE) is 22.9%. The maximum output power density (Pout) reaches 877 mW/mm at 2 GHz for our diamond FET. It is the best reported output power density for diamond FETs measured at 2 GHz[5, 10, 17, 20]. The Pout can be estimated by
where Ids-max is the maximum drain current density, Vwork is the drain voltage for the measurement of Pout, and Vknee is the knee voltage. The large-signal power gain result shows that the device exhibits a large compression even at class-A operation. The possible reasons are that the drain current density (323 mA/mm) is small, and the knee voltage (~6 V) is high for the H-terminated diamond FETs. The sheet resistance of the H-terminated diamond is high (~kΩ/□), and the parasitic resistance is high (poor Ohmic contact). Table 3 shows the compare of measured output power density and calculated output power density for the three diamond samples (I-PC, II-PC, and III-PC). The drain voltage values for the measurements of the three samples are –25, –24, and –25 V, respectively. It can be seen that for all three samples, the measured output power densities are lower than the calculated output power densities, which should be due to the trapping effects. The knee voltage will increase at continuous drain voltage and the drain current will degrade. Both of them would cause a decrease in output power. The II-PC sample shows the largest degrade in output power density. This is consistent with the pulsed I–V measurement. This sample shows the largest maximum drain current degeneration induced by drain-lag effect. These results indicate that defects and N impurities in the diamond act as traps in the carrier transport and have great influence on the output power characteristics of diamond FETs.