J. Semicond. > Volume 33 > Issue 1 > Article Number: 015001

A 3 to 5 GHz low-phase-noise fractional-N frequency synthesizer with adaptive frequency calibration for GSM/PCS/DCS/WCDMA transceivers

Pan Yaohua , Mei Niansong , Chen Hu , Huang Yumei and Hong Zhiliang

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Abstract: A low-phase-noise Σ-Δ fractional-N frequency synthesizer for GSM/PCS/DCS/WCDMA transceivers is presented. The voltage controlled oscillator is designed with a modified digital controlled capacitor array to extend the tuning range and minimize phase noise. A high-resolution adaptive frequency calibration technique is introduced to automatically choose frequency bands and increase phase-noise immunity. A prototype is implemented in 0.13 μm CMOS technology. The experimental results show that the designed 1.2 V wideband frequency synthesizer is locked from 3.05 to 5.17 GHz within 30 μs, which covers all five required frequency bands. The measured in-band phase noise are -89, -95.5 and -101 dBc/Hz for 3.8 GHz, 2 GHz and 948 MHz carriers, respectively, and accordingly the out-of-band phase noise are -121, -123 and -132 dBc/Hz at 1 MHz offset, which meet the phase-noise-mask requirements of the above-mentioned standards.

Key words: phase-locked loop

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Pan Y H, Mei N S, Chen H, Huang Y M, Hong Z L. A 3 to 5 GHz low-phase-noise fractional-N frequency synthesizer with adaptive frequency calibration for GSM/PCS/DCS/WCDMA transceivers[J]. J. Semicond., 2012, 33(1): 015001. doi: 10.1088/1674-4926/33/1/015001.

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History

Manuscript received: 20 August 2015 Manuscript revised: 13 August 2011 Online: Published: 01 January 2012

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