J. Semicond. > Volume 34 > Issue 3 > Article Number: 034003

A high-voltage SOI MOSFET with a compensation layer on the trenched buried oxide layer

Qiuming Zhao 1, , Qi Li 1, , , Ning Tang 1, and Yongchang Li 2,

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Abstract: A new silicon-on-insulator (SOI) high-voltage MOSFET structure with a compensation layer on the trenched buried oxide layer (CL T-LDMOS) is proposed. The high density inverse interface charges at the top surface of the buried oxide layer (BOX) enhance the electric field in the BOX and a uniform surface electric field profile is obtained, which results in the enhancement of the breakdown voltage (BV). The compensation layer can provide additional P-type charges, and the optimal drift region concentration is increased in order to satisfy the reduced surface electric field (RESURF) condition. The numerical simulation results indicate that the vertical electric field in the BOX increases to 6 MV/cm and the BV of the proposed device increases by 300% in comparison to a conventional SOI LDMOS, while maintaining low on-resistance.

Key words: trenched buried oxide layerbreakdown voltageon-resistancecompensation layer

Abstract: A new silicon-on-insulator (SOI) high-voltage MOSFET structure with a compensation layer on the trenched buried oxide layer (CL T-LDMOS) is proposed. The high density inverse interface charges at the top surface of the buried oxide layer (BOX) enhance the electric field in the BOX and a uniform surface electric field profile is obtained, which results in the enhancement of the breakdown voltage (BV). The compensation layer can provide additional P-type charges, and the optimal drift region concentration is increased in order to satisfy the reduced surface electric field (RESURF) condition. The numerical simulation results indicate that the vertical electric field in the BOX increases to 6 MV/cm and the BV of the proposed device increases by 300% in comparison to a conventional SOI LDMOS, while maintaining low on-resistance.

Key words: trenched buried oxide layerbreakdown voltageon-resistancecompensation layer



References:

[1]

Merchant S, Arnold E, Baumgart S. Realization of high breakdown voltage (> 700 V) in thin SOI device[J]. ISPSD, 1991: 31.

[2]

Li Q, Zhang B, Li Z. A new partial SOI high voltage device with double-faced step buried oxide structure[J]. Acta Physica Sinica, 2008, 57(10): 6565.

[3]

Ramakrishna T, Shyam H, Sankara E M. Realizing high breakdown voltage (> 600 V) in partial SOI technology[J]. Solid-State Electron, 2004, 48: 1655. doi: 10.1016/j.sse.2004.04.005

[4]

Luo X R, Li Z J, Zhang B. A novel structure and its breakdown mechanism of a SOI high voltage device with a shield trench[J]. Chinese Journal of Semiconductors, 2005, 26(11): 2154.

[5]

Zhang B, Li Z, Hu S. Field enhancement for dielectric layer of high-voltage devices on silicon on insulator[J]. IEEE Trans Electron Devices, 2009, 56(10): 2327. doi: 10.1109/TED.2009.2028405

[6]

Wang W L, Zhang B, Chen W J. High voltage SOI SJ-LDMOS with dynamic back-gate voltage[J]. Electron Lett, 2009, 45(4): 233. doi: 10.1049/el:20093005

[7]

Luo X, Zhang B, Li Z. A novel 700-V SOI LDMOS with double-sided trench[J]. IEEE Electron Device Lett, 2007, 28(5): 422. doi: 10.1109/LED.2007.894648

[8]

Ge R, Luo X, Jiang Y H. A low on-resistance SOI LDMOS using a trench gate and a recessed drain[J]. Journal of Semiconductors, 2012, 33(7): 074005. doi: 10.1088/1674-4926/33/7/074005

[1]

Merchant S, Arnold E, Baumgart S. Realization of high breakdown voltage (> 700 V) in thin SOI device[J]. ISPSD, 1991: 31.

[2]

Li Q, Zhang B, Li Z. A new partial SOI high voltage device with double-faced step buried oxide structure[J]. Acta Physica Sinica, 2008, 57(10): 6565.

[3]

Ramakrishna T, Shyam H, Sankara E M. Realizing high breakdown voltage (> 600 V) in partial SOI technology[J]. Solid-State Electron, 2004, 48: 1655. doi: 10.1016/j.sse.2004.04.005

[4]

Luo X R, Li Z J, Zhang B. A novel structure and its breakdown mechanism of a SOI high voltage device with a shield trench[J]. Chinese Journal of Semiconductors, 2005, 26(11): 2154.

[5]

Zhang B, Li Z, Hu S. Field enhancement for dielectric layer of high-voltage devices on silicon on insulator[J]. IEEE Trans Electron Devices, 2009, 56(10): 2327. doi: 10.1109/TED.2009.2028405

[6]

Wang W L, Zhang B, Chen W J. High voltage SOI SJ-LDMOS with dynamic back-gate voltage[J]. Electron Lett, 2009, 45(4): 233. doi: 10.1049/el:20093005

[7]

Luo X, Zhang B, Li Z. A novel 700-V SOI LDMOS with double-sided trench[J]. IEEE Electron Device Lett, 2007, 28(5): 422. doi: 10.1109/LED.2007.894648

[8]

Ge R, Luo X, Jiang Y H. A low on-resistance SOI LDMOS using a trench gate and a recessed drain[J]. Journal of Semiconductors, 2012, 33(7): 074005. doi: 10.1088/1674-4926/33/7/074005

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Q M Zhao, Q Li, N Tang, Y C Li. A high-voltage SOI MOSFET with a compensation layer on the trenched buried oxide layer[J]. J. Semicond., 2013, 34(3): 034003. doi: 10.1088/1674-4926/34/3/034003.

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Manuscript received: 02 July 2012 Manuscript revised: 26 September 2012 Online: Published: 01 March 2013

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