J. Semicond. > Volume 34 > Issue 8 > Article Number: 085007

A low power 2.4 GHz transceiver for ZigBee applications

Weiyang Liu , Jingjing Chen , Haiyong Wang and Nanjian Wu ,

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Abstract: This paper presents a low power 2.4 GHz transceiver for ZigBee applications. This transceiver adopts low power system architecture with a low-IF receiver and a direct-conversion transmitter. The receiver consists of a new low noise amplifier (LNA) with a noise cancellation function, a new inverter-based variable gain complex filter (VGCF) for image rejection, a passive quadrature mixer, and a decibel linear programmable gain amplifier (PGA). The transmitter adopts a quadrature mixer and a class-B mode variable gain power amplifier (PA) to reduce power consumption. This transceiver is implemented in 0.18 μm CMOS technology. The receiver achieves -95 dBm of sensitivity, 28 dBc of image rejection, and -8 dBm of third-order input intercept point (ⅡP3). The transmitter can deliver a maximum of +3 dBm output power with PA efficiency of 30%. The whole chip area is less than 4.32 mm2. It only consumes 12.63 mW in receiving mode and 14.22 mW in transmitting mode, respectively.

Key words: low powernoise cancellationquadrature mixertransceivervariable gain complex filter

Abstract: This paper presents a low power 2.4 GHz transceiver for ZigBee applications. This transceiver adopts low power system architecture with a low-IF receiver and a direct-conversion transmitter. The receiver consists of a new low noise amplifier (LNA) with a noise cancellation function, a new inverter-based variable gain complex filter (VGCF) for image rejection, a passive quadrature mixer, and a decibel linear programmable gain amplifier (PGA). The transmitter adopts a quadrature mixer and a class-B mode variable gain power amplifier (PA) to reduce power consumption. This transceiver is implemented in 0.18 μm CMOS technology. The receiver achieves -95 dBm of sensitivity, 28 dBc of image rejection, and -8 dBm of third-order input intercept point (ⅡP3). The transmitter can deliver a maximum of +3 dBm output power with PA efficiency of 30%. The whole chip area is less than 4.32 mm2. It only consumes 12.63 mW in receiving mode and 14.22 mW in transmitting mode, respectively.

Key words: low powernoise cancellationquadrature mixertransceivervariable gain complex filter



References:

[1]

IEEE Std 802. 15. 4-2003, IEEE Standard Part 15. 4: Wireless Medium access Control (MAC) and Physical Layer (PHY) specification for Wireless Personal Area Networks (WPANs)

[2]

Nguyen T K, Krizhanovskii V, Lee J. A low-power RF direct-conversion receiver/transmitter for 2.4-GHz-band IEEE 802.15.4 standard in 0.18-μm CMOS technology[J]. IEEE Trans Microw Theory Tech, 2006, 54(12): 4062. doi: 10.1109/TMTT.2006.885556

[3]

Eo Y S, Yu H J, Song S S. A fully integrated 2.4 GHz low IF CMOS transceiver for 802.15.4 ZigBee applications[J]. IEEE ASSCC Dig Tech Papers, 2007: 164.

[4]

Retz1 G, Shanan H, Mulvaney K. A highly integrated low-power 2.4 GHz transceiver using a direct-conversion diversity receiver in 0.18μm CMOS for IEEE 802.15.4 WPAN[J]. IEEE ISSCC Dig Tech Papers, 2009: 414.

[5]

Tedeschi M, Liscidini A, Castello R. Low-power quadrature receivers for ZigBee (IEEE 802.15.4) applications[J]. IEEE J Solid-State Circuits, 2010, 45: 1710. doi: 10.1109/JSSC.2010.2053861

[6]

Raja M K, Chen X, Yan D L. A 18 mW Tx, 22 mW Rx transceiver for 2.45 GHz IEEE 802.15.4 WPAN in 0.18-μm CMOS[J]. Proc IEEE Asian Solid-State Circuits Conf Tech Dig, 2010.

[7]

Yu R, Yeo T T. A 5.5 mA 2.4-GHz two-point modulation ZigBee transmitter with modulation gain calibration[J]. Proc IEEE CICC, 2009: 121.

[8]

Peng K C, Huang C H, Li C J. High-performance frequency-hopping transmitters using two-point delta-sigma modulation[J]. IEEE Trans Microw Theory Tech, 2004, 52(11): 2529. doi: 10.1109/TMTT.2004.837156

[9]

Kwon Y I, Park S G, Park T J. An ultra low-power CMOS transceiver using various low-power techniques for LR-WPAN applications[J]. IEEE Trans Circuits Syst Ⅰ, 2012, 59(2): 324. doi: 10.1109/TCSI.2011.2162463

[10]

Razavi B. Design considerations for direct conversion receivers[J]. IEEE Trans Circuits Syst Ⅱ:Analog Digit Signal Process, 1997, 44(6): 428. doi: 10.1109/82.592569

[11]

Lou Wenfeng, Feng Peng, Wang Haiyong. A low power fast-settling frequency-presetting PLL frequency synthesizer[J]. Journal of Semiconductors, 2012, 33(4): 045004. doi: 10.1088/1674-4926/33/4/045004

[12]

Feng P, Li Y, Wu N J. An ultra low power non-volatile memory in standard CMOS process for passive RFID tags[J]. IEEE Custom Integrated Circuit Conference, 2009: 713.

[13]

Bruccoleri F, Klumperink E A M, Nauta B. Wide-band CMOS low-noise amplifier exploiting thermal noise canceling[J]. IEEE J Solid-State Circuits, 2004, 39: 275. doi: 10.1109/JSSC.2003.821786

[14]

Belostotski L, Haslett J W. Noise figure optimization of induc-tively degenerated CMOS LNAs with integrated gate inductors[J]. IEEE Trans Circuits Syst, 2006, 53(3): 1409.

[15]

Guthrie B, Hughes J, Sayers T. A CMOS gyrator low-IF filter for a dual-mode Bluetooth/ZigBee transceiver[J]. IEEE J Solid-State Circuits, 2005, 40(9): 1872. doi: 10.1109/JSSC.2005.848146

[16]

Nauta B. A CMOS transconductance-C filter technique for very high frequencies[J]. IEEE J Solid-State Circuits, 1992, 27: 142. doi: 10.1109/4.127337

[17]

Sowlati T, Leenaerts D M W. A 2.4-GHz 0.18-μm CMOS self-biased cascode power amplifier[J]. IEEE Journal of Solid-State Circuits, 2003, 38(8): 1318. doi: 10.1109/JSSC.2003.814417

[18]

Balankutty A, Yu S A, Feng Y. A 0.6-V zero-IF/low-IF receiver with integrated fractional-N synthesizer for 2.4-GHz ISM-band applications[J]. IEEE J Solid-State Circuits, 2010, 45(3): 538. doi: 10.1109/JSSC.2009.2039827

[1]

IEEE Std 802. 15. 4-2003, IEEE Standard Part 15. 4: Wireless Medium access Control (MAC) and Physical Layer (PHY) specification for Wireless Personal Area Networks (WPANs)

[2]

Nguyen T K, Krizhanovskii V, Lee J. A low-power RF direct-conversion receiver/transmitter for 2.4-GHz-band IEEE 802.15.4 standard in 0.18-μm CMOS technology[J]. IEEE Trans Microw Theory Tech, 2006, 54(12): 4062. doi: 10.1109/TMTT.2006.885556

[3]

Eo Y S, Yu H J, Song S S. A fully integrated 2.4 GHz low IF CMOS transceiver for 802.15.4 ZigBee applications[J]. IEEE ASSCC Dig Tech Papers, 2007: 164.

[4]

Retz1 G, Shanan H, Mulvaney K. A highly integrated low-power 2.4 GHz transceiver using a direct-conversion diversity receiver in 0.18μm CMOS for IEEE 802.15.4 WPAN[J]. IEEE ISSCC Dig Tech Papers, 2009: 414.

[5]

Tedeschi M, Liscidini A, Castello R. Low-power quadrature receivers for ZigBee (IEEE 802.15.4) applications[J]. IEEE J Solid-State Circuits, 2010, 45: 1710. doi: 10.1109/JSSC.2010.2053861

[6]

Raja M K, Chen X, Yan D L. A 18 mW Tx, 22 mW Rx transceiver for 2.45 GHz IEEE 802.15.4 WPAN in 0.18-μm CMOS[J]. Proc IEEE Asian Solid-State Circuits Conf Tech Dig, 2010.

[7]

Yu R, Yeo T T. A 5.5 mA 2.4-GHz two-point modulation ZigBee transmitter with modulation gain calibration[J]. Proc IEEE CICC, 2009: 121.

[8]

Peng K C, Huang C H, Li C J. High-performance frequency-hopping transmitters using two-point delta-sigma modulation[J]. IEEE Trans Microw Theory Tech, 2004, 52(11): 2529. doi: 10.1109/TMTT.2004.837156

[9]

Kwon Y I, Park S G, Park T J. An ultra low-power CMOS transceiver using various low-power techniques for LR-WPAN applications[J]. IEEE Trans Circuits Syst Ⅰ, 2012, 59(2): 324. doi: 10.1109/TCSI.2011.2162463

[10]

Razavi B. Design considerations for direct conversion receivers[J]. IEEE Trans Circuits Syst Ⅱ:Analog Digit Signal Process, 1997, 44(6): 428. doi: 10.1109/82.592569

[11]

Lou Wenfeng, Feng Peng, Wang Haiyong. A low power fast-settling frequency-presetting PLL frequency synthesizer[J]. Journal of Semiconductors, 2012, 33(4): 045004. doi: 10.1088/1674-4926/33/4/045004

[12]

Feng P, Li Y, Wu N J. An ultra low power non-volatile memory in standard CMOS process for passive RFID tags[J]. IEEE Custom Integrated Circuit Conference, 2009: 713.

[13]

Bruccoleri F, Klumperink E A M, Nauta B. Wide-band CMOS low-noise amplifier exploiting thermal noise canceling[J]. IEEE J Solid-State Circuits, 2004, 39: 275. doi: 10.1109/JSSC.2003.821786

[14]

Belostotski L, Haslett J W. Noise figure optimization of induc-tively degenerated CMOS LNAs with integrated gate inductors[J]. IEEE Trans Circuits Syst, 2006, 53(3): 1409.

[15]

Guthrie B, Hughes J, Sayers T. A CMOS gyrator low-IF filter for a dual-mode Bluetooth/ZigBee transceiver[J]. IEEE J Solid-State Circuits, 2005, 40(9): 1872. doi: 10.1109/JSSC.2005.848146

[16]

Nauta B. A CMOS transconductance-C filter technique for very high frequencies[J]. IEEE J Solid-State Circuits, 1992, 27: 142. doi: 10.1109/4.127337

[17]

Sowlati T, Leenaerts D M W. A 2.4-GHz 0.18-μm CMOS self-biased cascode power amplifier[J]. IEEE Journal of Solid-State Circuits, 2003, 38(8): 1318. doi: 10.1109/JSSC.2003.814417

[18]

Balankutty A, Yu S A, Feng Y. A 0.6-V zero-IF/low-IF receiver with integrated fractional-N synthesizer for 2.4-GHz ISM-band applications[J]. IEEE J Solid-State Circuits, 2010, 45(3): 538. doi: 10.1109/JSSC.2009.2039827

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W Y Liu, J J Chen, H Y Wang, N J Wu. A low power 2.4 GHz transceiver for ZigBee applications[J]. J. Semicond., 2013, 34(8): 085007. doi: 10.1088/1674-4926/34/8/085007.

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Manuscript received: 21 January 2013 Manuscript revised: 01 February 2013 Online: Published: 01 August 2013

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