Fig. 1.
Load capacitance and its components.
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| Citation: |
Vijay Kumar Sharma, Manisha Pattanaik. VLSI scaling methods and low power CMOS buffer circuit[J]. Journal of Semiconductors, 2013, 34(9): 095001. doi: 10.1088/1674-4926/34/9/095001
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V K Sharma, M Pattanaik. VLSI scaling methods and low power CMOS buffer circuit[J]. J. Semicond., 2013, 34(9): 095001. doi: 10.1088/1674-4926/34/9/095001.
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VLSI scaling methods and low power CMOS buffer circuit
DOI: 10.1088/1674-4926/34/9/095001
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Abstract
Device scaling is an important part of the very large scale integration (VLSI) design to boost up the success path of VLSI industry, which results in denser and faster integration of the devices. As technology node moves towards the very deep submicron region, leakage current and circuit reliability become the key issues. Both are increasing with the new technology generation and affecting the performance of the overall logic circuit. The VLSI designers must keep the balance in power dissipation and the circuit's performance with scaling of the devices. In this paper, different scaling methods are studied first. These scaling methods are used to identify the effects of those scaling methods on the power dissipation and propagation delay of the CMOS buffer circuit. For mitigating the power dissipation in scaled devices, we have proposed a reliable leakage reduction low power transmission gate (LPTG) approach and tested it on complementary metal oxide semiconductor (CMOS) buffer circuit. All simulation results are taken on HSPICE tool with Berkeley predictive technology model (BPTM) BSIM4 bulk CMOS files. The LPTG CMOS buffer reduces 95.16% power dissipation with 84.20% improvement in figure of merit at 32 nm technology node. Various process, voltage and temperature variations are analyzed for proving the robustness of the proposed approach. Leakage current uncertainty decreases from 0.91 to 0.43 in the CMOS buffer circuit that causes large circuit reliability. -
References
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