C L Wang, S X Diao, F J Lin. A low-power time-domain VCO-based ADC in 65 nm CMOS[J]. J. Semicond., 2014, 35(10): 105009. doi: 10.1088/1674-4926/35/10/105009.
Chenluan Wang^{ } , Shengxi Diao^{ , } and Fujiang Lin^{ }
Abstract: A low-power, high-FoM (figure of merit), time-domain VCO (voltage controlled oscillator)-based ADC (analog-to-digital converter) in 65 nm CMOS technology is proposed. An asynchronous sigma-delta modulator (ASDM) is used to convert the voltage input signal to a square wave time signal, where the information is contained in its pulse-width. A time-domain quantizer, which uses VCO to convert voltage to frequency, is adopted, while the XOR (exclusive-OR) gate circuits convert the frequency information to digital representatives. The ASDM does not need an external clock, so there is no quantization noise. At the same time, the ASDM applies a harmonic-distortion-cancellation technique to its transconductance stage, which increases the SNDR (signal to noise and distortion ratio) performance of the ASDM. Since the output of the ASDM is a two-level voltage signal, the VCO's V-F(voltage to frequency) conversion curve is always linear. The XOR phase quantizer has an inherent feature of first-order noise-shaping. It puts the ADC's low-frequency output noise to high-frequency which is further filtered out by a low-pass filter. The proposed ADC achieves an SNR/SNDR of 54. dB/54.3 dB in the 8 MHz bandwidth, while consuming 2.8 mW. The FoM of the proposed ADC is a 334 fJ/conv-step.
Key words: VCO, ADC, ASDM, PWM (pulse width modulation), nonlinearity, low-power
Abstract: A low-power, high-FoM (figure of merit), time-domain VCO (voltage controlled oscillator)-based ADC (analog-to-digital converter) in 65 nm CMOS technology is proposed. An asynchronous sigma-delta modulator (ASDM) is used to convert the voltage input signal to a square wave time signal, where the information is contained in its pulse-width. A time-domain quantizer, which uses VCO to convert voltage to frequency, is adopted, while the XOR (exclusive-OR) gate circuits convert the frequency information to digital representatives. The ASDM does not need an external clock, so there is no quantization noise. At the same time, the ASDM applies a harmonic-distortion-cancellation technique to its transconductance stage, which increases the SNDR (signal to noise and distortion ratio) performance of the ASDM. Since the output of the ASDM is a two-level voltage signal, the VCO's V-F(voltage to frequency) conversion curve is always linear. The XOR phase quantizer has an inherent feature of first-order noise-shaping. It puts the ADC's low-frequency output noise to high-frequency which is further filtered out by a low-pass filter. The proposed ADC achieves an SNR/SNDR of 54. dB/54.3 dB in the 8 MHz bandwidth, while consuming 2.8 mW. The FoM of the proposed ADC is a 334 fJ/conv-step.
Key words:
VCO, ADC, ASDM, PWM (pulse width modulation), nonlinearity, low-power
References:
[1] |
Park M, Perrott M H. A 78 dB SNDR 87 mW 20 MHz bandwidth continuous-time delta-sigma ADC with VCO-based integrator and quantizer implemented in 0.13μm CMOS[J]. IEEE J Solid-State Circuits, 2009, 44(12): 3344. doi: 10.1109/JSSC.2009.2032703 |
[2] |
Taylor G, Galton I. A mostly-digital variable-rate continuous-time delta-sigma modulator ADC[J]. IEEE J Solid-State Circuits, 2010, 45(12): 2634. doi: 10.1109/JSSC.2010.2073193 |
[3] |
Rao S, Young B, Elshazly A, et al. A 71 dB SFDR open loop VCO-based ADC using 2-level PWM modulation. Symposium of VLSI Circuits Digest, 2011 |
[4] |
Daniels J, Dehaene W, Steyaert M S J, et al. A/D conversion using asynchronous delta-sigma modulation and time-to-digital conversion. IEEE Trans Circuits Syst I Regular Papers, 2010, 57: 2404 |
[5] |
Reddy K, Rao S, Inti R, et al. A 16 mW 78 dB-SNDR 10 MHz-BW CT-δ σ ADC using residue-cancelling VCO-based quantizer. ISSCC Digest Technical Papers, 2012 |
[6] |
Ouzounov S, Roza E, Hegt J A. Analysis and design of high-performance asynchronous sigma-delta modulators with a binary quantizer[J]. IEEE J Solid-State Circuits, 2005, 41(3): 588. |
[7] |
Kim J, Jang T K, Yoon Y G. Analysis and design of voltage-controlled oscillator based analog-to-digital converter[J]. IEEE Trans Circuits Syst I:Regular Papers, 2010, 1(57): 18. |
[8] |
Ouzounov S, Roza E, Weide G V D. A CMOS V-I converter with 75-dB SFDR and 360μW power consumption[J]. IEEE J Solid-State Circuits, 2005, 40(7): 1527. doi: 10.1109/JSSC.2005.847496 |
[9] |
Ma Zhaoxin, Bai Xuefei, Huang Lu. Design of a delay-locked-loop-based time-to-digital converter[J]. Journal of Semiconductors, 2013, 34(9): 095003. doi: 10.1088/1674-4926/34/9/095003 |
[1] |
Park M, Perrott M H. A 78 dB SNDR 87 mW 20 MHz bandwidth continuous-time delta-sigma ADC with VCO-based integrator and quantizer implemented in 0.13μm CMOS[J]. IEEE J Solid-State Circuits, 2009, 44(12): 3344. doi: 10.1109/JSSC.2009.2032703 |
[2] |
Taylor G, Galton I. A mostly-digital variable-rate continuous-time delta-sigma modulator ADC[J]. IEEE J Solid-State Circuits, 2010, 45(12): 2634. doi: 10.1109/JSSC.2010.2073193 |
[3] |
Rao S, Young B, Elshazly A, et al. A 71 dB SFDR open loop VCO-based ADC using 2-level PWM modulation. Symposium of VLSI Circuits Digest, 2011 |
[4] |
Daniels J, Dehaene W, Steyaert M S J, et al. A/D conversion using asynchronous delta-sigma modulation and time-to-digital conversion. IEEE Trans Circuits Syst I Regular Papers, 2010, 57: 2404 |
[5] |
Reddy K, Rao S, Inti R, et al. A 16 mW 78 dB-SNDR 10 MHz-BW CT-δ σ ADC using residue-cancelling VCO-based quantizer. ISSCC Digest Technical Papers, 2012 |
[6] |
Ouzounov S, Roza E, Hegt J A. Analysis and design of high-performance asynchronous sigma-delta modulators with a binary quantizer[J]. IEEE J Solid-State Circuits, 2005, 41(3): 588. |
[7] |
Kim J, Jang T K, Yoon Y G. Analysis and design of voltage-controlled oscillator based analog-to-digital converter[J]. IEEE Trans Circuits Syst I:Regular Papers, 2010, 1(57): 18. |
[8] |
Ouzounov S, Roza E, Weide G V D. A CMOS V-I converter with 75-dB SFDR and 360μW power consumption[J]. IEEE J Solid-State Circuits, 2005, 40(7): 1527. doi: 10.1109/JSSC.2005.847496 |
[9] |
Ma Zhaoxin, Bai Xuefei, Huang Lu. Design of a delay-locked-loop-based time-to-digital converter[J]. Journal of Semiconductors, 2013, 34(9): 095003. doi: 10.1088/1674-4926/34/9/095003 |
[1] |
Zhixiong Sheng, Fengqi Yu. A low-power current self-adjusted VCO using a bottom PMOS current source. J. Semicond., 2014, 35(9): 095006. doi: 10.1088/1674-4926/35/9/095006 |
[2] |
Chenghao Bian, Jun Yan, Yin Shi, Ling Sun. A 130 nm CMOS low-power SAR ADC for wide-band communication systems. J. Semicond., 2014, 35(2): 025003. doi: 10.1088/1674-4926/35/2/025003 |
[3] |
Wang Shaodong, Gao Xuebang, Wu Hongjiang, Wang Xiangwei, Mo Lidong. A 12~18GHz Wide Band VCO Based on Quasi-MMIC. J. Semicond., 2008, 29(1): 63. |
[4] |
Ting Yan, Yuming Zhang, Hongliang Lü, Yimen Zhang, Yue Wu, Yifeng Liu. Low phase noise GaAs HBT VCO in Ka-band. J. Semicond., 2015, 36(2): 025001. doi: 10.1088/1674-4926/36/2/025001 |
[5] |
Nan Chen, Shengxi Diao, Lu Huang, Xuefei Bai, Fujiang Lin. Design optimizations of phase noise, power consumption and frequency tuning for VCO. J. Semicond., 2013, 34(9): 095009. doi: 10.1088/1674-4926/34/9/095009 |
[6] |
Zhang Li, Chi Baoyong, Yao Jinke, Wang Zhihua, Chen Hongyi. A 2GHz Low Power Differentially Tuned CMOS Monolithic LC-VCO. J. Semicond., 2006, 27(9): 1543. |
[7] |
Wang Xiantai, Shen Huajun, Jin Zhi, Chen Yanhu, Liu Xinyu. A 6 GHz high power and low phase noise VCO using an InGaP/GaAs HBT. J. Semicond., 2009, 30(2): 025005. doi: 10.1088/1674-4926/30/2/025005 |
[8] |
Song Ying, Wang Yuan, Jia Song, Zhao Baoying. A VCO sub-band selection circuit for fast PLL calibration. J. Semicond., 2009, 30(8): 085010. doi: 10.1088/1674-4926/30/8/085010 |
[9] |
Xu Conghui, Xi Jingtian, Lu Lei, Yang Yuqing, Tan Xi, Yan Na, Min Hao. A 4.2–5 GHz, low phase noise LC-VCO with constant bandwidth and small tuning gain. J. Semicond., 2009, 30(9): 095002. doi: 10.1088/1674-4926/30/9/095002 |
[10] |
Zhang Jian, Chen Liqiang, Li Zhiqiang, Chen Pufeng, Zhang Haiying. Design of a 2.5GHz Low Phase-Noise LC-VCO in 0.35μm SiGe BiCMOS. J. Semicond., 2008, 29(5): 827. |
[11] |
Li Zhenrong, Zhuang Yiqi, Li Bing, Jin Gang, Jin Zhao. A 2.4 GHz high-linearity low-phase-noise CMOS LC-VCO based on capacitance compensation. J. Semicond., 2010, 31(7): 075005. doi: 10.1088/1674-4926/31/7/075005 |
[12] |
Yinkun Huang, Danyu Wu, Lei Zhou, Fan Jiang, Jin Wu, Zhi Jin. A 23 GHz low power VCO in SiGe BiCMOS technology. J. Semicond., 2013, 34(4): 045003. doi: 10.1088/1674-4926/34/4/045003 |
[13] |
Peng Yunfeng, Zhou Feng. A Novel Sampling Switch Suitable for Low-Voltage Analog-to-Digital Converters. J. Semicond., 2006, 27(8): 1367. |
[14] |
Nie Zedong, Zhang Fengjuan, Li Jie, Wang Lei. Low-power digital ASIC for on-chip spectral analysis of low-frequency physiological signals. J. Semicond., 2012, 33(6): 065004. doi: 10.1088/1674-4926/33/6/065004 |
[15] |
He Yan, Hu Jianyun, Min Hao. An Ultralow-Voltage,Low-Power Baseband Processor for UHF RFID Tags. J. Semicond., 2006, 27(10): 1866. |
[16] |
Wu Ahui. 30GHz PHEMT Oscillator. J. Semicond., 2005, 26(S1): 252. |
[17] |
Kai Tang, Qiao Meng, Zhigong Wang, Yi Zhang, Kuai Yin, Ting Guo. A low-power 20 GSps track-and-hold amplifier in 0.18 μm SiGe BiCMOS technology. J. Semicond., 2013, 34(9): 095002. doi: 10.1088/1674-4926/34/9/095002 |
[18] |
Kai Tang, Qiao Meng, Zhigong Wang, Ting Guo. A low power 20 GHz comparator in 90 nm COMS technology. J. Semicond., 2014, 35(5): 055002. doi: 10.1088/1674-4926/35/5/055002 |
[19] |
Liu Yongwang, Wang Zhigong, Li Wei. 1.244GHz 0.25μm CMOS Low-Power Phase-Locked Loop. J. Semicond., 2006, 27(12): 2190. |
[20] |
Wang Zhuping, Zhong Shun'an, Ding Yingtao, Wang Xiaoqing. Design and implementation of a low-pass filter for microsensor signal processing. J. Semicond., 2010, 31(12): 125002. doi: 10.1088/1674-4926/31/12/125002 |
C L Wang, S X Diao, F J Lin. A low-power time-domain VCO-based ADC in 65 nm CMOS[J]. J. Semicond., 2014, 35(10): 105009. doi: 10.1088/1674-4926/35/10/105009.
Article views: 1033 Times PDF downloads: 10 Times Cited by: 0 Times
Manuscript received: 28 March 2014 Manuscript revised: 07 May 2014 Online: Published: 01 October 2014
Journal of Semiconductors © 2017 All Rights Reserved äº¬ICPå¤05085259å·-2