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Volume 35, Issue 10, Oct 2014

# SEMICONDUCTOR PHYSICS

• ## Properties of polaron in a triangular quantum well induced by the Rashba effect

J. Semicond.  2014, 35(10): 102001

doi: 10.1088/1674-4926/35/10/102001

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The properties of the weakly-coupling bound polaron, considering an influence of Rashba effect, which is brought about by the spin-orbit (SO) interaction, in an semiconductor triangular quantum well (TQW), have been studied by using the linear combination operator and the unitary transformation methods. We obtain an expression for the ground state energy of the weak-coupling and bound polaron in a TQW as a function of the coupling constant, Coulomb bound potential, and the electron areal density. Our numerical results show that the ground state energy of the polaron is composed of four parts, one part is caused by the electrons' own energy, the second part is caused by the Rashba effect, the third part occurs because of the Coulomb bound potential, and the last term is induced by the interaction between the electrons and LO phonons. The interactions between the orbit and the spin with different directions have different effects on the ground state energy of the polaron.

• ## First-principles study on the synergistic effects of codoped anatase TiO2 photocatalysts codoped with N/V or C/Cr

J. Semicond.  2014, 35(10): 102002

doi: 10.1088/1674-4926/35/10/102002

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An effective compensated codoping approach is described to modify the photoelectrochemical properties of anatase TiO2 by doping with nonmetals (N or C) and transition metals (V or Cr) impurities. Here, compensated codoped TiO2 systems are constructed with different dopant species and sources, and then their dopant formation energies and electronic structures are performed to study the stability and visible-light photoactivity by first-principles plane-wave ultrasoft pseudopotential calculations, respectively. The calculated results demonstrate that the codoping with transition metals facilitates the enhancement of the concentration of p-type dopants (N and C) in a host lattice. Especially, compensated codoping not only reduces the energy gap, to enhance the optical absorption, and eliminate the local trapping, to improve carrier mobility and conversion efficiency, but it also keeps the oxidation-reduction potential of the conduction band edge. These results are conducive to the understanding of the synergistic mechanism of the photocatalytic activity of TiO2 that is enhanced by codoping.

• # SEMICONDUCTOR MATERIALS

• ## A combined experimental-computational study on nitrogen doped Cu2O as the wide-spectrum absorption material

J. Semicond.  2014, 35(10): 103001

doi: 10.1088/1674-4926/35/10/103001

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Highly-oriented Cu2O thin films were prepared by low temperature thermal oxidation of evaporated Cu thin films. The films were doped with different doses of nitrogen by ion implantation. An absorption peak appears below the absorption edge in the absorption spectrum of highly nitrogen doped Cu2O. The effect of nitrogen doping on the crystal structure, electronic structure and optical properties of Cu2O were investigated systematically by first-principles calculations. The calculation results indicate that an intermediate energy band exists in the forbidden gap of highly nitrogen doped Cu2O. The electron transition from the valence band to the intermediate band is consistent with the absorption peak by experimental observation. Experimental and computational results indicate that nitrogen doped Cu2O could be a suitable absorbing material candidate for wide-spectrum detectors or intermediate band solar cells.

• ## Charge storage characteristics of Ni nanocrystals formed by synchronous crystallization

J. Semicond.  2014, 35(10): 103002

doi: 10.1088/1674-4926/35/10/103002

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The rapid thermal annealing (RTA) nano-crystallization method is widely used in the metal nanocrystal fabrication process. However, the high temperature (usually 600-900℃) in the RTA process will worsen the performance and reliability of devices. A novel method has been proposed to grow metal nanocrystal by synchronous in situ nano-crystallization of metal thin film (SINC), which is able to resolve the problems mentioned above. Compared with Ni nanocrystals (NCs) formed by RTA, Ni NCs prepared by SINC can obtain more energy to crystallize, and its crystallization temperature is greatly reduced. A large memory window (2.78 V) was observed for Ni NCs deposited by SINC at 300℃. However, the largest window is only 1.26 V for Ni NCs formed by RTA at 600℃. A large change (from 0.20 to 4.59 V) of the memory window was observed while the operation voltage increased from 0 to ±10 V, which is due to an occurrence of strong carrier trapping in Ni NCs. Flat-band voltage shift rapidly increases to its saturation value, which indicates that electron/hole trapping in Ni NCs mainly occurs at the initial stage of the program/erase process. A theoretical model was proposed to characterize the charging and discharging processes.

• ## Te doped ultrabroad band tunnel junction

J. Semicond.  2014, 35(10): 103003

doi: 10.1088/1674-4926/35/10/103003

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A GaInP/AlGaAs broadband tunnel junction (TJ) with a peak current density of 65.3 A/cm2 and an AlGaInP/AlGaAs ultrabroad band TJ with a peak current density of 6.1 A/cm2 were studied and fabricated. Diethyltellurium (DETe) was chosen as an n-type dopant in the TJ. The growth temperature, valve switching and flow variation parameters of DETe were studied for better performance. Measurements, including predoping of DETe before growth and heating up reactor temperature after growth, were taken to deal with the effect of turn-on and off of tellurium. The strain balance method was used to the manage lattice mismatch that was introduced by the tellurium. Various flows of DETe were studied to get the appropriate value needed to fabricate a high peak current density tunnel junction.

• # SEMICONDUCTOR DEVICES

• ## Model development for analyzing 2DEG sheet charge density and threshold voltage considering interface DOS for AlInN/GaN MOSHEMT

J. Semicond.  2014, 35(10): 104001

doi: 10.1088/1674-4926/35/10/104001

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A model predicting the behavior of various parameters, such as 2DEG sheet charge density and threshold voltage, with the variation of barrier thickness and oxide thickness considering interface density of states is presented. The mathematical dependence of these parameters is derived in conjunction with the interface density of states. The dependence of sheet charge density with the barrier thickness and with the oxide thickness is plotted and an insight into the barrier scaling properties of AlInN based MOSHEMTs is presented. The threshold voltage is also plotted with respect to barrier thickness and oxide thickness, which reveals the possibility of the enhancement mode operation of the device at low values of the interface DOS. The results are in good agreement with the fabricated device available in the literature.

• ## Analytical model for subthreshold current and subthreshold swing of short-channel double-material-gate MOSFETs with strained-silicon channel on silicon-germanium substrates

J. Semicond.  2014, 35(10): 104002

doi: 10.1088/1674-4926/35/10/104002

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The present work gives some insight into the subthreshold behaviour of short-channel double-material-gate strained-silicon on silicon-germanium MOSFETs in terms of subthreshold swing and off-current. The formulation of subthreshold current and, thereupon, the subthreshold swing have been done by exploiting the expression of potential distribution in the channel region of the device. The dependence of the subthreshold characteristics on the device parameters, such as Ge mole fraction, gate length ratio, work function of control gate metal and gate length, has been tested in detail. The analytical models have been validated by the numerical simulation results that were obtained from the device simulation software ATLASTM by Silvaco Inc.

• ## Self-heating and traps effects on the drain transient response of AlGaN/GaN HEMTs

J. Semicond.  2014, 35(10): 104003

doi: 10.1088/1674-4926/35/10/104003

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The effects of self-heating and traps on the drain current transient responses of AlGaN/GaN HEMTs are studied by 2D numerical simulation. The variation of the drain current simulated by the drain turn-on pulses has been analyzed. Our results show that temperature is the main factor for the drain current lag. The time that the drain current takes to reach a steady state depends on the thermal time constant, which is 80 μs in this case. The dynamics of the trapping of electron and channel electron density under drain turn-on pulse voltage are discussed in detail, which indicates that the accepter traps in the buffer are the major reason for the current collapse when the electric field significantly changes. The channel electron density has been shown to increase as the channel temperature rises.

• ## ADO-phosphonic acid self-assembled monolayer modified dielectrics for organic thin film transistors

J. Semicond.  2014, 35(10): 104004

doi: 10.1088/1674-4926/35/10/104004

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This study explores a strategy of using the phosphonic acid derivative (11-((12-(anthracen-2-yl)dodecyl)oxy)-11-oxoundecyl) phosphonic acid (ADO-phosphonic acid) as self-assembled monolayers (SAMs) on a Si/SiO2 surface to induce the crystallization of rubrene in vacuum deposited thin film transistors, which showed a field-effect mobility as high as 0.18 cm2/(V·s). It is found that ADO-phosphonic acid SAMs play a unique role in modulating the morphology of rubrene to form a crystalline film in the thin-film transistors.

• ## Simulations of backgate sandwich nanowire MOSFETs with improved device performance

J. Semicond.  2014, 35(10): 104005

doi: 10.1088/1674-4926/35/10/104005

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We propose a novel backgate sandwich nanowire MOSFET (SNFET), which offers the advantages of ETSOI (dynamic backgate voltage controllability) and nanowire FETs (good short channel effect). A backgate is used for threshold voltage (Vt) control of the SNFET. Compared with a backgate FinFET with a punch-through stop layer (PTSL), the SNFET possesses improved device performance. 3D device simulations indicate that the SNFET has a three times larger overdrive current, a~75% smaller off leakage current, and reduced subthreshold swing (SS) and DIBL than those of a backgate FinFET when the nanowire (NW) and the fin are of equal width. A new process flow to fabricate the backgate SNFET is also proposed in this work. Our analytical model suggests that Vt control by the backgate can be attributed to the capacitances formed by the frontgate, NW, and backgate. The SNFET devices are compatible with the latest state-of-the-art high-k/metal gate CMOS technology with the unique capability of independent backgate control for nFETs and pFETs, which is promising for sub-22 nm scaling down.

• ## A novel multiple super junction power device structure with low specific on-resistance

J. Semicond.  2014, 35(10): 104006

doi: 10.1088/1674-4926/35/10/104006

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A novel multiple super junction (MSJ) LDMOS power device is proposed to decrease Ron due to lateral and vertical interactions between the N-pillar and P-pillar. In the studied device:multiple layers of SJ are introduced oppositely under surface SJ; when compared with 2D-depleting of the conventional super junction (CSJ), a 3D-depleted effect is formed in the MSJ thanks to vertical electric field modulation; and, current distribution is improved by deep drain, which increases the drift doping concentration and results in a lower on-resistance. The high electric field around the drain region by substrate-assisted depleted effect is reduced due to the charge balance result from the electric field shielding effect of the bottom SJ, which causes the uniform electric field in the drift region and the high breakdown voltage. The numerical simulation results indicate that the specific on-resistance of the MSJ device is reduced by 42% compared with that of CSJ device, while maintaining a high breakdown voltage; the cell pitch of the device is 12 μm.

• ## Simulation study of conductive filament growth dynamics in oxide-electrolyte-based ReRAM

J. Semicond.  2014, 35(10): 104007

doi: 10.1088/1674-4926/35/10/104007

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Monte Carlo (MC) simulations, including multiple physical and chemical mechanisms, were performed to investigate the microstructure evolution of a conducting metal filament in a typical oxide-electrolyte-based ReRAM. It has been revealed that the growth direction and geometry of the conductive filament are controlled by the ion migration rate in the electrolyte layer during the formation procedure. When the migration rate is relative high, the filament is shown to grow from cathode to anode. When the migration rate is low, the growth direction is expected to start from the anode. Simulated conductive filament (CF) geometries and Ⅰ-Ⅴ characteristics are also illustrated and analyzed. A good agreement between the simulation results and experiment data is obtained.

• ## Cantilever with immobilized antibody for liver cancer biomarker detection

J. Semicond.  2014, 35(10): 104008

doi: 10.1088/1674-4926/35/10/104008

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A novel cantilever array-based bio-sensor was batch-fabricated with IC compatible MEMS technology for precise liver cancer bio-marker detection. A micro-cavity was designed in the free end of the cantilever for local antibody-immobilization, thus the adsorption of the cancer biomarker takes place only in the local region of the cantilever instead of the whole lever, and the effect of adsorption-induced \begin{document}$k$\end{document} variation can be dramatically reduced. These structural features offer several advantages:high sensitivity, high throughput, high mass detection accuracy, and a portable system. In addition, an analytical model has been established to eliminate the effect of the adsorption-induced lever stiffness change and has been applied to the precise mass detection of the cancer biomarker AFP; the experimentally detected AFP antigen mass by the sensor (7.6 pg/mL) is quite close to the calculated one (5.5 pg/mL), two orders of magnitude better than those of the fully antibody-immobilized cantilever sensor. These approaches can promote real applications of the cantilever sensors in cancer diagnosis.

• ## Room temperature quantum cascade detector operating at 4.3 μm

J. Semicond.  2014, 35(10): 104009

doi: 10.1088/1674-4926/35/10/104009

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A strain-compensated InP-based InGaAs/InAlAs quantum cascade detector grown by solid source molecular beam epitaxy is demonstrated. The device operates at 4.3 μm up to room temperature (300 K) with a responsivity of 1.27 mA/W and a Johnson noise limited detectivity of 1.02×107 cm·Hz1/2/W. At 80 K, the responsivity and detectivity are 14.55 mA/W and 1.26×1010 cm·Hz1/2/W, respectively. According to the response range, this detector is much suitable for greenhouse gas detection.

• ## Monolithic integration of a silica-based 16-channel VMUX/VDMUX on quartz substrate

J. Semicond.  2014, 35(10): 104010

doi: 10.1088/1674-4926/35/10/104010

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A monolithic integrated variable attenuator multiplexer/demultiplexer is demonstrated. It is composed of a 16-channel 200 GHz silica-based arrayed waveguide grating and an array of Mach-Zehnder interferometer thermo-optic variable optical attenuators. The integrated device is fabricated on a quartz substrate, which eliminates the process of depositing the undercladding layer and reduces the power consumption compared with a device fabricated on a silicon substrate. The insertion loss and crosstalk of the integrated device are -5 dB and less than -22 dB, respectively. The power consumption is only 110 mW at the attenuation of 20 dB per channel.

• ## An electro-optic directed decoder based on two cascaded microring resonators

J. Semicond.  2014, 35(10): 104011

doi: 10.1088/1674-4926/35/10/104011

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We demonstrate a directed optical decoder device consisting of two cascaded microring resonators, which are both modulated through the plasma dispersion effect. The inherent resonance wavelength mismatch between two microring resonators caused by fabrication errors is compensated for by using microheaters that are fabricated on top of the microring resonators. Two electrical signals generated by pulse pattern generators are used to modulate the PIN diodes that are embedded in the device, and the results are presented by optical signals detected at the four output ports of the device. The working wavelength and driving voltages of two MRRs are measured and analyzed by the static response spectra of the device. Dynamic experimental results show that the decoding operation is achieved at a speed of 100 Mbps.

J. Semicond.  2014, 35(10): 104012

doi: 10.1088/1674-4926/35/10/104012

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According to the multi-performance degradation of the bipolar transistor in the accelerating storage process, an extrapolation model of the storage lifetime is proposed. In this model, using the Wiener process simulates the mono-degradation process of each feature degradation; using the copula function describes the correlation among these feature degradations. The Wiener process and parameters in the copula function are considered to associate with the temperature, and their relationships can be represented by the converted equations. Through the maximum likelihood estimation, the parameters in the Wiener process can be found; introducing Kendall's tau, those in the copula function can be estimated. By conducting the regression analyses of the estimated values of the parameters in each stress, their corresponding converted equations can be shown. Based on the storage test data of bipolar transistors, with the estimation method, the storage lifetime is found. The findings show that the model is reasonable for the prediction of storage lifetime.

• # SEMICONDUCTOR INTEGRATED CIRCUITS

• ## An inductorless CMOS programmable-gain amplifier with a > 3 GHz bandwidth for 60 GHz wireless transceivers

J. Semicond.  2014, 35(10): 105001

doi: 10.1088/1674-4926/35/10/105001

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An inductorless wideband programmable-gain amplifier (PGA) for 60 GHz wireless transceivers is presented. To attain wideband characteristics, a modified Cherry-Hooper amplifier with a negative capacitive neutralization technique is employed as the gain cell while a novel circuit technique for gain adjustment is adopted; this technique can be universally applicable in wideband PGA design and greatly simplifying the design of wideband PGA. By cascading two gain cells and an output buffer stage, the PGA achieves the highest gain of 30 dB with the bandwidth much wider than 3 GHz. The PGA has been integrated into one whole 60 GHz wireless transceiver and implemented in the TSMC 65 nm CMOS process. The measurements on the receiver front-end show that the receiver front-end achieves an 18 dB variable gain range with a > 3 GHz bandwidth, which proves the proposed PGA achieves an 18 dB variable gain range with a bandwidth much wider than 3 GHz. The PGA consumes 10.7 mW of power from a 1.2-V supply voltage with a core area of only 0.025 mm2.

• ## Design and analysis of 20 Gb/s inductorless limiting amplifier in 65 nm CMOS technology

J. Semicond.  2014, 35(10): 105002

doi: 10.1088/1674-4926/35/10/105002

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A high speed inductorless limiting amplifier (LA) in an optical communication receiver with the working speed up to 20 Gb/s is presented. The LA includes an input matching network, a four-stage 3rd order amplifier core, an output buffer for the test and a DC offset cancellation (DCOC). It uses the active interleaving feedback technique both to broaden the bandwidth and achieve the flatness response. Based on our careful analysis of the DCOC and stability, an error amplifier is added to the DCOC loop in order to keep the offset voltage reasonable. Fabricated in the 65 nm CMOS technology, the LA only occupies an area of 0.45×0.25 mm2 (without PAD). The measurement results show that the LA achieves a differential voltage gain of 37 dB, and a 3-dB bandwidth of 16.5 GHz. Up to 26.5 GHz, the Sdd11 and Sdd22 are less than -16 dB and -9 dB. The chip excluding buffer is supplied by 1.2 V VDD and draws a current of 50 mA.

• ## Lower-power, high-linearity class-AB current-mode programmable gain amplifier

J. Semicond.  2014, 35(10): 105003

doi: 10.1088/1674-4926/35/10/105003

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A novel class-AB implementation of a current-mode programmable gain amplifier (CPGA) including a current-mode DC offset cancellation loop is presented. The proposed CPGA is based on a current amplifier and provides a current gain in a range of 40 dB with a 1 dB step. The CPGA is characterized by a wide range of current gain variation, a lower power dissipation, and a small chip size. The proposed circuit is fabricated using a 0.18 μm CMOS technology. The CPGA draws a current of less than 2.52 mA from a 1.8 V supply while occupying an active area of 0.099 μm2. The measured results show an overall gain variation from 10 to 50 dB with a gain error of less than 0.40 dB. The OP1dB varies from 11.80 to 13.71 dBm, and the 3 dB bandwidth varies from 22.2 to 34.7 MHz over the whole gain range.

• ## A 2.52-mW continuous-time Σ Δ modulator with 72 dB dynamic range for FM radio

J. Semicond.  2014, 35(10): 105004

doi: 10.1088/1674-4926/35/10/105004

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A continuous-time Σ Δ modulator with a third-order loop filter and a 3-bit quantizer is realized. The modulator is robust to the excess loop delay, clock jitter, and RC product variations. When designing the integrator, an op-amp with novel GBW extension structure, improving the linearity of the loop filter, is adopted. The prototype chip is designed in a 130 nm CMOS technology, targeting FM radio applications. The experimental results show that the prototype modulator achieves a 72 dB dynamic range and a 70.7 dB signal to noise and distortion ratio over a 500 kHz bandwidth with a 26 MHz clock, consuming 2.52 mW power from a 1.2 V supply.

• ## Ka-band full-360° analog phase shifter with low insertion loss

J. Semicond.  2014, 35(10): 105005

doi: 10.1088/1674-4926/35/10/105005

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A new reflection-type wideband 360° monolithic-microwave integrated-circuit (MMIC) analog phase shifter at the Ka-band is proposed. The phase shifter is designed based on the principle of vector synthesis. Three Lange couplers are employed in the phase shifter, which is fabricated by the standard 0.25-μm GaAs process. We use four 4×40 μm GaAs HEMTs as the reflection loads. A microstrip line in parallel with the device is used as an inductance to counteract the parasitic capacitance of the device so that the reflection load performs like a pure resistance and the insertion loss can be decreased. In this phase shifter, a folded Lange coupler is utilized to reduce the size of the chip. The size of the proposed MMIC phase shifter is only 2.0×1.2 mm2. The measurement results show that the insertion loss is 5.0 ±0.8 dB and a 360° continuously tunable range across 27-32 GHz is obtained with miniscule DC power consumption.

• ## Design of improved CMOS phase-frequency detector and charge-pump for phase-locked loop

J. Semicond.  2014, 35(10): 105006

doi: 10.1088/1674-4926/35/10/105006

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Two essential blocks for the PLLs based on CP, a phase-frequency detector (PFD) and an improved current steering charge-pump (CP), are developed. The mechanisms for widening the phase error detection range and eliminating the dead zone are analyzed and applied in our design to optimize the proposed PFD. To obtain excellent current matching and minimum current variation over a wide output voltage range, an improved structure for the proposed CP is developed by fully utilizing many additional sub-circuits. Implemented in a standard 90-nm CMOS process, the proposed PFD achieves a phase error detection range from -354 ° to 354 ° and the improved CP demonstrates a current mismatch of less than 1.1% and a pump-current variation of 4% across the output voltage, swinging from 0.2 to 1.1 V, and the power consumption is 1.3 mW under a 1.2-V supply.

• ## A reconfigurable 256 × 256 image sensor controller that is compatible for depth measurement

J. Semicond.  2014, 35(10): 105007

doi: 10.1088/1674-4926/35/10/105007

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This paper presents an image sensor controller that is compatible for depth measurement, which is based on the continuous-wave modulation time-of-flight technology. The image sensor controller is utilized to generate reconfigurable control signals for a 256×256 high speed CMOS image sensor with a conventional image sensing mode and a depth measurement mode. The image sensor controller generates control signals for the pixel array to realize the rolling exposure and the correlated double sampling functions. An refined circuit design technique in the logic level is presented to reduce chip area and power consumption. The chip, with a size of 700×3380 μm2, is fabricated in a standard 0.18 μm CMOS image sensor process. The power consumption estimated by the synthesis tool is 65 mW under a 1.8 V supply voltage and a 100 MHz clock frequency. Our test results show that the image sensor controller functions properly.

• ## A 12-bit compact column-parallel SAR ADC with dynamic power control technique for high-speed CMOS image sensors

J. Semicond.  2014, 35(10): 105008

doi: 10.1088/1674-4926/35/10/105008

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This paper presents a 12-bit column-parallel successive approximation register analog-to-digital converter (SAR ADC) for high-speed CMOS image sensors. A segmented binary-weighted switched capacitor digital-to-analog converter (CDAC) and a staggered structure MOM unit capacitor is used to reduce the ADC area and to make its layout fit double pixel pitches. An electrical field shielding layout method is proposed to eliminate the parasitic capacitance on the top plate of the unit capacitor. A dynamic power control technique is proposed to reduce the power consumption of a single channel during readout. An off-chip foreground digital calibration is adopted to compensate for the nonlinearity due to the mismatch of unit capacitors among the CDAC. The prototype SAR ADC is fabricated in a 0.18 μm 1P5M CIS process. A single SAR ADC occupies 20×2020 μm2. Sampling at 833 kS/s, the measured differential nonlinearity, integral nonlinearity and effective number of bits of SAR ADC with calibration are 0.9/-1 LSB, 1/-1.1 LSB and 11.24 bits, respectively; the power consumption is only 0.26 mW under a 1.8-V supply and decreases linearly as the frame rate decreases.

• ## A low-power time-domain VCO-based ADC in 65 nm CMOS

J. Semicond.  2014, 35(10): 105009

doi: 10.1088/1674-4926/35/10/105009

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A low-power, high-FoM (figure of merit), time-domain VCO (voltage controlled oscillator)-based ADC (analog-to-digital converter) in 65 nm CMOS technology is proposed. An asynchronous sigma-delta modulator (ASDM) is used to convert the voltage input signal to a square wave time signal, where the information is contained in its pulse-width. A time-domain quantizer, which uses VCO to convert voltage to frequency, is adopted, while the XOR (exclusive-OR) gate circuits convert the frequency information to digital representatives. The ASDM does not need an external clock, so there is no quantization noise. At the same time, the ASDM applies a harmonic-distortion-cancellation technique to its transconductance stage, which increases the SNDR (signal to noise and distortion ratio) performance of the ASDM. Since the output of the ASDM is a two-level voltage signal, the VCO's V-F(voltage to frequency) conversion curve is always linear. The XOR phase quantizer has an inherent feature of first-order noise-shaping. It puts the ADC's low-frequency output noise to high-frequency which is further filtered out by a low-pass filter. The proposed ADC achieves an SNR/SNDR of 54. dB/54.3 dB in the 8 MHz bandwidth, while consuming 2.8 mW. The FoM of the proposed ADC is a 334 fJ/conv-step.

• ## Design and implementation of a high sensitivity fully integrated passive UHF RFID tag

J. Semicond.  2014, 35(10): 105010

doi: 10.1088/1674-4926/35/10/105010

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A fully integrated passive UHF RFID tag complying with the ISO18000-6B protocol is presented, which includes an analog front-end, a baseband processor, and an EEPROM memory. To extend the communication range, a high efficiency differential-drive CMOS rectifier is adopted. A novel high performance voltage limiter is used to provide a stable limiting voltage, with a 172 mV voltage variation against temperature variation and process dispersion. The dynamic band-enhancement technique is used in the regulator circuit to improve the regulating capacity. A rail-to-rail hysteresis comparator is adopted to demodulate the signal correctly in any condition. The whole transponder chip is implemented in a 0.18 μm CMOS process, with a die size of 900 × 800 μm2. Our measurement results show that the total power consumption of the tag chip is only 6.8 μW, with a sensitivity of -13.5 dBm.

• ## Design and analysis of a dual mode CMOS field programmable analog array

J. Semicond.  2014, 35(10): 105011

doi: 10.1088/1674-4926/35/10/105011

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This paper presents a novel field-programmable analog array (FPAA) architecture featuring a dual mode including discrete-time (DT) and continuous-time (CT) operation modes, along with a highly routable connection boxes (CBs) based interconnection lattice. The dual mode circuit for the FPAA is capable of achieving targeted optimal performance in different applications. The architecture utilizes routing switches in a CB not only for the signal interconnection purpose but also for control of the electrical charge transfer required in switched-capacitor circuits. This way, the performance of the circuit in either mode shall not be hampered with adding of programmability. The proposed FPAA is designed and implemented in a 0.18 μm standard CMOS process with a 3.3 V supply voltage. The result from post-layout simulation shows that a maximum bandwidth of 265 MHz through the interconnection network is achieved. The measured results from demonstrated examples show that the maximum signal bandwidth of up to 2 MHz in CT mode is obtained with the spurious free dynamic range of 54 dB, while the signal processing precision in DT mode reaches 96.4%.

• ## An implantable neurostimulator with an integrated high-voltage inductive power-recovery frontend

J. Semicond.  2014, 35(10): 105012

doi: 10.1088/1674-4926/35/10/105012

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This paper present a highly-integrated neurostimulator with an on-chip inductive power-recovery frontend and high-voltage stimulus generator. In particular, the power-recovery frontend includes a high-voltage full-wave rectifier (up to 100 V AC input), high-voltage series regulators (24/5 V outputs) and a linear regulator (1.8/3.3 V output) with bandgap voltage reference. With the high voltage output of the series regulator, the proposed neurostimulator could deliver a considerably large current in high electrode-tissue contact impedance. This neurostimulator has been fabricated in a CSMC 1 μm 5/40/700 V BCD process and the total silicon area including pads is 5.8 mm2. Preliminary tests are successful as the neurostimulator shows good stability under a 13.56 MHz AC supply. Compared to previously reported works, our design has advantages of a wide induced voltage range (26-100 V), high output voltage (up to 24 V) and high-level integration, which are suitable for implantable neurostimulators.

• ## A 410 μW, 70 dB SNR high performance analog front-end for portable audio application

J. Semicond.  2014, 35(10): 105013

doi: 10.1088/1674-4926/35/10/105013

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This paper describes an analog front-end (AFE) intended for portable audio application, which operates at 1 V and consumes only 410 μW. The AFE consists of a 30 dB-gain programmable gain amplifier (PGA) and a 2nd-order 3-bit sigma-delta modulator. The PGA with single input and on-chip common-mode bias voltage shows good noise-reduction performance. The modulator makes use of data weighted averaging to reduce the linearity requirements of the digital-to-analog converter in the feedback loop. The AFE is implemented in the SMIC 0.13 μm 1P8M CMOS process. The measurement results show that in a 1 V power supply, at 200 mVp-p, between 100 Hz and 20 kHz, the maximal signal-to-noise ratio is 70 dB, and the total power is 410 μW.

• ## An ultralow power wireless intraocular pressure monitoring system

J. Semicond.  2014, 35(10): 105014

doi: 10.1088/1674-4926/35/10/105014

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This paper describes an ultralow power wireless intraocular pressure (IOP) monitoring system that is dedicated to sensing and transferring intraocular pressure of glaucoma patients. Our system is comprised of a capacitive pressure sensor, an application-specific integrated circuit, which is designed on the SMIC 180 nm process, and a dipole antenna. The system is wirelessly powered and demonstrates a power consumption of 7.56 μW at 1.24 V during continuous monitoring, a significant reduction in active power dissipation compared to existing work. The input RF sensitivity is -13 dBm. A significant reduction in input RF sensitivity results from the reduction of mismatch time of the ASK modulation caused by FM0 encoding. The system exhibits an average error of ±1.5 mmHg in measured pressure. Finally, a complete IOP system is demonstrated in the real biological environment, showing a successful reading of the pressure of an eye.

• # SEMICONDUCTOR TECHNOLOGY

• ## Combining a multi deposition multi annealing technique with a scavenging (Ti) to improve the high-k/metal gate stack performance for a gate-last process

J. Semicond.  2014, 35(10): 106001

doi: 10.1088/1674-4926/35/10/106001

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ALD HfO2 films fabricated by a novel multi deposition multi annealing (MDMA) technique are investigated, we have included samples both with and without a Ti scavenging layer. As compared to the reference gate stack treated by conventional one-time deposition and annealing (D & A), devices receiving MDMA show a significant reduction in leakage current. Meanwhile, EOT growth is effectively controlled by the Ti scavenging layer. This improvement strongly correlates with the cycle number of D & A (while keeping the total annealing time and total dielectrics thickness the same). Transmission electron microscope and energy-dispersive X-ray spectroscopy analysis suggests that oxygen incorporation into both the high-k film and the interfacial layer is likely to be responsible for the improvement of the device. This novel MDMA is promising for the development of gate stack technology in a gate last integration scheme.

• ## The effects of process condition of Top-TiN and TaN thickness on the effective work function of MOSCAP with high-k/metal gate stacks

J. Semicond.  2014, 35(10): 106002

doi: 10.1088/1674-4926/35/10/106002

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We introduced a TaN/TiAl/top-TiN triple-layer to modulate the effective work function of a TiN-based metal gate stack by varying the TaN thickness and top-TiN technology process. The results show that a thinner TaN and PVD-process top-TiN capping provide smaller effective work function (EWF), and a thicker TaN and ALD-process top-TiN capping provides a larger EWF; here, the EWF shifts are from 4.25 to 4.56 eV. A physical understanding of the dependence of the EWF on the top-TiN technology process and TaN thickness is proposed. Compared with PVD-TiN room temperature process, the ALD-TiN 400℃ process provides more thermal budget. It would also promote more Al atoms to diffuse into the top-TiN rather than the bottom-TiN. Meanwhile, the thicker TaN prevents the Al atoms diffusing into the bottom-TiN. These facts induce the EWF to increase.

• ## Slurry components of TiO2 thin film in chemical mechanical polishing

J. Semicond.  2014, 35(10): 106003

doi: 10.1088/1674-4926/35/10/106003

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A chemical mechanical polishing (CMP) process was selected to smooth TiO2 thin film surface and improve the removal rate. Meanwhile, the optimal process conditions were used in TiO2 thin film CMP. The effects of silica sols concentration, slurry pH, chelating agent and active agent concentration on surface roughness and material removal rate were investigated. Our experimental results indicated that we got lower surface roughness (1.26 Å, the scanned area was 10×10 μm2) and higher polishing rate (65.6 nm/min), the optimal parameters were:silica sols concentration 8.0%, pH value 9.0, active agent concentration 50 mL/L, chelating agent concentration 10 mL/L, respectively.