J. Semicond. > Volume 35 > Issue 5 > Article Number: 055001

FDTD based transition time dependent crosstalk analysis for coupled RLC interconnects

Devendra Kumar Sharma 1, , , Brajesh Kumar Kaushik 2, and R.K. Sharma 3,

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Abstract: The performance of high density chips operating in the GHz range is mostly affected by on-chip interconnects. The interconnect delay depends on many factors, a few of them are inputs toggling patterns, line & coupling parasitics, input rise/fall time and source/load characteristics. The transition time of the input is of prime importance in high speed circuits. This paper addresses the FDTD based analysis of transition time effects on functional and dynamic crosstalk. The analysis is carried out for equal and unequal transition times of coupled inputs. The analysis of the effects of unequal rise time is equally important because practically, it is quite common to have mismatching in the rise time of the signals transmitting through different length wires. To demonstrate the effects, two distributed RLC lines coupled inductively and capacitively are taken into consideration. The FDTD technique is used because it gives accurate results and carries time domain analysis of coupled lines. The number of lumps in SPICE simulations is considered the same as those of spatial segments. To validate the FDTD computed results, SPICE simulations are run and results are compared. A good agreement of the computed results has been observed with respect to SPICE simulated results. An average error of less than 3.2% is observed in the computation of the performance parameters using the proposed method.

Key words: FDTDtransition timecrosstalk noisedelaycoupled interconnects

Abstract: The performance of high density chips operating in the GHz range is mostly affected by on-chip interconnects. The interconnect delay depends on many factors, a few of them are inputs toggling patterns, line & coupling parasitics, input rise/fall time and source/load characteristics. The transition time of the input is of prime importance in high speed circuits. This paper addresses the FDTD based analysis of transition time effects on functional and dynamic crosstalk. The analysis is carried out for equal and unequal transition times of coupled inputs. The analysis of the effects of unequal rise time is equally important because practically, it is quite common to have mismatching in the rise time of the signals transmitting through different length wires. To demonstrate the effects, two distributed RLC lines coupled inductively and capacitively are taken into consideration. The FDTD technique is used because it gives accurate results and carries time domain analysis of coupled lines. The number of lumps in SPICE simulations is considered the same as those of spatial segments. To validate the FDTD computed results, SPICE simulations are run and results are compared. A good agreement of the computed results has been observed with respect to SPICE simulated results. An average error of less than 3.2% is observed in the computation of the performance parameters using the proposed method.

Key words: FDTDtransition timecrosstalk noisedelaycoupled interconnects



References:

[1]

Rabaey J M. Digital integrated circuits: a design perspective. Prentice-Hall, Englewood Cliffs, N. J. , 1996

[2]

Bakoglu H B. Circuits, interconnections and packaging for VLSI. Reading, MA: Addison-Wesley, 1990

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Agarwal K, Sylvester D, Blaauw D. Modeling and analysis of crosstalk noise is coupled RLC interconnects[J]. IEEE Trans Computer-Aided Design of Integrated Circuits and Systems, 2006, 25(5): 892. doi: 10.1109/TCAD.2005.855961

[5]

Kaushik B K, Sarkar S, Agarwal R P. Effect of line resistance and driver width on crosstalk in coupled VLSI interconnects[J]. Microelectronics International, 2007, 24(3): 42. doi: 10.1108/13565360710779181

[6]

Roy A, Mohmoud N, Chowdhury M H. Effects of coupling capacitance and inductance on delay uncertainty and clock skew[J]. Design Automation Conf, 2007: 184.

[7]

Kang S M, Leblebici Y. CMOS digital integrated circuits-analysis and design. TMH, New York, 2003

[8]

Roy A, Xu J, Chowdhury M H. Analysis of the impacts of signal slew and skew on the behavior of coupled RLC interconnects for different switching patterns[J]. IEEE Trans VLSI Syst, 2010, 18(2): 338. doi: 10.1109/TVLSI.2008.2011911

[9]

Kaushik B K, Sarkar S, Agarwal R P. Crosstalk analysis and repeater insertion in crosstalk aware coupled VLSI interconnects[J]. Microelectronics International, 2006, 23(3): 55. doi: 10.1108/13565360610680776

[10]

Sharma D K, Kaushik B K, Sharma R K. Effect of equal and mismatched signal transition time on power dissipation in global VLSI interconnects[J]. International Journal of VLSI Design and Communication Systems, 2012, 3(4): 111. doi: 10.5121/vlsic

[11]

Sharma D K, Kaushik B K, Sharma R K. Effect of coupling parasitics and CMOS driver width on transition time for dynamic inputs. International Journal of Electronics, 2013, DOI: DOI:10.1080/00207217.2013.794485

[12]

Li X C, Mao J F, Swaminathan M. Transient analysis of CMOS-gate driven RLCG interconnects based on FDTD[J]. IEEE Trans Computer-Aided Design of Integrated Circuits and Systems, 2011, 30(4): 574. doi: 10.1109/TCAD.2010.2095650

[13]

Afrooz K, Abdipour A, Tavakoli A, et al. Time domain analysis of lossy nonuniform transmission line using FDTD technique. Proc Asia-Pacific Conf Applied Electromagnetics, 2007

[14]

Sharma D K, Mittal S, Kaushik B K. Dynamic crosstalk analysis in RLC modeled interconnects using FDTD method[J]. IEEE Intl Conf Computer and Communication Technology (ICCCT), 2012: 326.

[15]

Ismail Y I, Friedman E G. Figures of merit to characterize the importance of on-chip inductance[J]. IEEE Trans VLSI Syst, 1999, 7(4): 442. doi: 10.1109/92.805751

[16]

Deutsch A, Kopcsay G V, Restle P J. When are transmission-line effects important for on-chip interconnections[J]. IEEE Trans Microw Theory Tech, 1997, 45(10): 1836. doi: 10.1109/22.641781

[17]

Paul C R. Analysis of multiconductor transmission lines. NY: Wily Interscience, 1994

[18]

Paul C R. Incorporation of terminal constraints in the FDTD analysis of transmission lines[J]. IEEE Trans Electromag Compatibility, 1994, 36(2): 85. doi: 10.1109/15.293284

[1]

Rabaey J M. Digital integrated circuits: a design perspective. Prentice-Hall, Englewood Cliffs, N. J. , 1996

[2]

Bakoglu H B. Circuits, interconnections and packaging for VLSI. Reading, MA: Addison-Wesley, 1990

[3]

Elgamel M A, Bayoumi M A. Interconnect noise analysis and optimization in deep submicron technology. IEEE Circuits Syst Mag, 2003, Fourth Quarter: 6

[4]

Agarwal K, Sylvester D, Blaauw D. Modeling and analysis of crosstalk noise is coupled RLC interconnects[J]. IEEE Trans Computer-Aided Design of Integrated Circuits and Systems, 2006, 25(5): 892. doi: 10.1109/TCAD.2005.855961

[5]

Kaushik B K, Sarkar S, Agarwal R P. Effect of line resistance and driver width on crosstalk in coupled VLSI interconnects[J]. Microelectronics International, 2007, 24(3): 42. doi: 10.1108/13565360710779181

[6]

Roy A, Mohmoud N, Chowdhury M H. Effects of coupling capacitance and inductance on delay uncertainty and clock skew[J]. Design Automation Conf, 2007: 184.

[7]

Kang S M, Leblebici Y. CMOS digital integrated circuits-analysis and design. TMH, New York, 2003

[8]

Roy A, Xu J, Chowdhury M H. Analysis of the impacts of signal slew and skew on the behavior of coupled RLC interconnects for different switching patterns[J]. IEEE Trans VLSI Syst, 2010, 18(2): 338. doi: 10.1109/TVLSI.2008.2011911

[9]

Kaushik B K, Sarkar S, Agarwal R P. Crosstalk analysis and repeater insertion in crosstalk aware coupled VLSI interconnects[J]. Microelectronics International, 2006, 23(3): 55. doi: 10.1108/13565360610680776

[10]

Sharma D K, Kaushik B K, Sharma R K. Effect of equal and mismatched signal transition time on power dissipation in global VLSI interconnects[J]. International Journal of VLSI Design and Communication Systems, 2012, 3(4): 111. doi: 10.5121/vlsic

[11]

Sharma D K, Kaushik B K, Sharma R K. Effect of coupling parasitics and CMOS driver width on transition time for dynamic inputs. International Journal of Electronics, 2013, DOI: DOI:10.1080/00207217.2013.794485

[12]

Li X C, Mao J F, Swaminathan M. Transient analysis of CMOS-gate driven RLCG interconnects based on FDTD[J]. IEEE Trans Computer-Aided Design of Integrated Circuits and Systems, 2011, 30(4): 574. doi: 10.1109/TCAD.2010.2095650

[13]

Afrooz K, Abdipour A, Tavakoli A, et al. Time domain analysis of lossy nonuniform transmission line using FDTD technique. Proc Asia-Pacific Conf Applied Electromagnetics, 2007

[14]

Sharma D K, Mittal S, Kaushik B K. Dynamic crosstalk analysis in RLC modeled interconnects using FDTD method[J]. IEEE Intl Conf Computer and Communication Technology (ICCCT), 2012: 326.

[15]

Ismail Y I, Friedman E G. Figures of merit to characterize the importance of on-chip inductance[J]. IEEE Trans VLSI Syst, 1999, 7(4): 442. doi: 10.1109/92.805751

[16]

Deutsch A, Kopcsay G V, Restle P J. When are transmission-line effects important for on-chip interconnections[J]. IEEE Trans Microw Theory Tech, 1997, 45(10): 1836. doi: 10.1109/22.641781

[17]

Paul C R. Analysis of multiconductor transmission lines. NY: Wily Interscience, 1994

[18]

Paul C R. Incorporation of terminal constraints in the FDTD analysis of transmission lines[J]. IEEE Trans Electromag Compatibility, 1994, 36(2): 85. doi: 10.1109/15.293284

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D K Sharma, B K Kaushik, R.K. Sharma. FDTD based transition time dependent crosstalk analysis for coupled RLC interconnects[J]. J. Semicond., 2014, 35(5): 055001. doi: 10.1088/1674-4926/35/5/055001.

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Manuscript received: 30 September 2013 Manuscript revised: Online: Published: 01 May 2014

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