J. Semicond. > Volume 35 > Issue 5 > Article Number: 055002

A low power 20 GHz comparator in 90 nm COMS technology

Kai Tang 1, 2, , Qiao Meng 1, 2, , , Zhigong Wang 1, 2, and Ting Guo 1, 2,

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Abstract: A low power 20 GHz CMOS dynamic latched regeneration comparator for ultra-high-speed, low-power analog-to-digital converters (ADCs) is proposed. The time constant in both the tracking and regeneration phases of the latch are analyzed based on the small signal model. A dynamic source-common logic (SCL) topology is adopted in the master-slave latch to increase the tracking and regeneration speeds. Implemented in 90 nm CMOS technology, this comparator only occupies a die area of 65×150 μm2 with a power dissipation of 14 mW from a 1.2 V power supply. The measurement results show that the comparator can work up to 20 GHz. Operating with an input frequency of 1 GHz, the circuit can oversample up to 20 Giga-sampling-per-second (GSps) with 5 bits resolution; while operating at Nyquist, the comparator can sample up to 20 GSps with 4 bits resolution. The comparator has been successfully used in a 20 GSps flash ADC and the circuit can be also used in other high speed applications.

Key words: comparatorADCultra-high-speedlow powerlatchCMOS

Abstract: A low power 20 GHz CMOS dynamic latched regeneration comparator for ultra-high-speed, low-power analog-to-digital converters (ADCs) is proposed. The time constant in both the tracking and regeneration phases of the latch are analyzed based on the small signal model. A dynamic source-common logic (SCL) topology is adopted in the master-slave latch to increase the tracking and regeneration speeds. Implemented in 90 nm CMOS technology, this comparator only occupies a die area of 65×150 μm2 with a power dissipation of 14 mW from a 1.2 V power supply. The measurement results show that the comparator can work up to 20 GHz. Operating with an input frequency of 1 GHz, the circuit can oversample up to 20 Giga-sampling-per-second (GSps) with 5 bits resolution; while operating at Nyquist, the comparator can sample up to 20 GSps with 4 bits resolution. The comparator has been successfully used in a 20 GSps flash ADC and the circuit can be also used in other high speed applications.

Key words: comparatorADCultra-high-speedlow powerlatchCMOS



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[1]

Kuo W M L, Li X, Krithivasan R. A 32 Gsample/sec SiGe HBT comparator for ultra-high-speed analog-to-digital conversion[J]. APMC, 2005: 4.

[2]

Kraus S, Kallfass I, Makon R E. A 20-GHz bipolar latched comparator with improved sensitivity implemented in InP HBT technology[J]. IEEE Trans Microw Theory Tech, 2011, 59(3): 707. doi: 10.1109/TMTT.2011.2104974

[3]

Huang Zhenxing, Zhou Lei, Su Yongbo. A 20-GHz ultra-high-speed InP DHBT comparator[J]. Journal of Semiconductors, 2012, 33(7): 075003. doi: 10.1088/1674-4926/33/7/075003

[4]

Zhou Lei, Wu Danyu, Chen Jianwu. 12.5 Gbps 1:16 DEMUX IC with high speed synchronizing circuits[J]. Journal of Semiconductors, 2011, 32(12): 125010. doi: 10.1088/1674-4926/32/12/125010

[5]

Shohreh G, Andre C, Salama T. Track-and-hold and comparator for a 12. 5 GS/s, 8 bit ADC. IEEE International Midwest Symposium on Circuits and System, 2009: 353

[6]

Goll B, Zimmermann H. A 65 nm CMOS comparator with modified latch to achieve 7 GHz/1.3 mW at 1.2 V and 700 MHz/47μW at 0.6 V[J]. ISSCC, 2009: 328.

[7]

Schvan P, Bach J, Fait C. A 24 GS/s 6 b ADC in 90 nm CMOS[J]. ISSCC, 2008: 544.

[8]

Okaniwa Y, Tamura H, Kibune M. A 40-Gb/s CMOS clocked comparator with bandwidth modulation technique[J]. IEEE J Solid-State Circuits, 2005, 40(8): 1680. doi: 10.1109/JSSC.2005.852014

[9]

Fan X P, Chan P K. A CMOS high-speed multistage preamplifier for comparator design[J]. ISCAS, 2004: 545.

[10]

Doernberg J, Gray P R, Hodges D A. A 10-bit 5-Msample/s CMOS two-step flash ADC[J]. IEEE J Solid-State Circuits, 1989, 24(2): 241. doi: 10.1109/4.18582

[11]

Shirai E. CMOS multistage preamplifier design for high-speed and high-resolution comparators[J]. IEEE Trans Circuits Syst Ⅱ, 2007, 54(2): 166. doi: 10.1109/TCSII.2006.883091

[12]

Li X, Kuo W M L, Lu Y. A 7-bit, 18 GHz SiGe HBT comparator for medium resolution A/D conversion[J]. Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting, 2005: 144.

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K Tang, Q Meng, Z G Wang, T Guo. A low power 20 GHz comparator in 90 nm COMS technology[J]. J. Semicond., 2014, 35(5): 055002. doi: 10.1088/1674-4926/35/5/055002.

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Manuscript received: 12 October 2013 Manuscript revised: 20 December 2013 Online: Published: 01 May 2014

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